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Searched refs:__REG32 (Results 1 – 24 of 24) sorted by relevance

/bsp/raspberry-pi/raspi3-64/driver/
A Draspi.h135 #define IRQ_PEND1 __REG32(IRQ_BASE + 0x0004)
136 #define IRQ_PEND2 __REG32(IRQ_BASE + 0x0008)
138 #define IRQ_ENABLE1 __REG32(IRQ_BASE + 0x0010)
139 #define IRQ_ENABLE2 __REG32(IRQ_BASE + 0x0014)
141 #define IRQ_DISABLE1 __REG32(IRQ_BASE + 0x001C)
142 #define IRQ_DISABLE2 __REG32(IRQ_BASE + 0x0020)
148 #define PM_RSTC __REG32(PM_BASE + 0x001C)
149 #define PM_RSTS __REG32(PM_BASE + 0x0020)
150 #define PM_WDOG __REG32(PM_BASE + 0x0024)
163 #define STIMER_CS __REG32(STIMER_BASE + 0x0000)
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/bsp/loongson/ls1cdev/drivers/
A Ddisplay_controller.h22 #define DC_FB_CONFIG __REG32(DC_BASE + 0x000)
23 #define DC_FB_BUFFER_ADDR0 __REG32(DC_BASE + 0x020)
24 #define DC_FB_BUFFER_STRIDE __REG32(DC_BASE + 0x040)
25 #define DC_FB_BUFFER_ORIGIN __REG32(DC_BASE + 0x060)
26 #define DC_DITHER_CONFIG __REG32(DC_BASE + 0x120)
27 #define DC_DITHER_TABLE_LOW __REG32(DC_BASE + 0x140)
28 #define DC_DITHER_TABLE_HIGH __REG32(DC_BASE + 0x160)
29 #define DC_PANEL_CONFIG __REG32(DC_BASE + 0x180)
30 #define DC_PANEL_TIMING __REG32(DC_BASE + 0x1A0)
31 #define DC_HDISPLAY __REG32(DC_BASE + 0x1C0)
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A Dtouch.c312 #define TOUCH_INT_EN __REG32(LS1C_INT4_EN)
/bsp/raspberry-pi/raspi4-32/driver/
A Ddrv_dma.h24 #define DMA_INT_STATUS_REG __REG32(DMA_INT_STATUS)
25 #define DMA_ENABLE_REG __REG32(DMA_ENABLE)
27 #define DMA_CS(dch) __REG32(DMA_BASE + dch*0x100 + 0x000) /* Control and Status …
35 #define DMA_DEBUG(dch) __REG32(DMA_BASE + dch*0x100 + 0x01c) /* Debug */
38 #define DMA15_CS __REG32(DMA15_BASE + 0x000) /* Control and Status */
39 #define DMA15_CONBLK_AD __REG32(DMA15_BASE + 0x004) /* Control Block Address */
41 #define DMA15_SOURCE_AD __REG32(DMA15_BASE + 0x00c) /* CB Word 1(Source Address) */
43 #define DMA15_TXFR_LEN __REG32(DMA15_BASE + 0x014) /* CB Word 3(Transfer Length) */
44 #define DMA15_STRIDE __REG32(DMA15_BASE + 0x018) /* CB Word 4(2D Stride) */
45 #define DMA15_NEXTCONBK __REG32(DMA15_BASE + 0x01c) /* CB Word 5(Next CB Address) */
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A Ddrv_i2c.h16 #define BSC_C(BASE) __REG32(BASE + 0x0000) /* BSC Master Control */
17 #define BSC_S(BASE) __REG32(BASE + 0x0004) /* BSC Master Status */
18 #define BSC_DLEN(BASE) __REG32(BASE + 0x0008) /* BSC Master Data Length */
19 #define BSC_A(BASE) __REG32(BASE + 0x000c) /* BSC Master Slave Address */
20 #define BSC_FIFO(BASE) __REG32(BASE + 0x0010) /* BSC Master Data FIFO */
21 #define BSC_DIV(BASE) __REG32(BASE + 0x0014) /* BSC Master Clock Divider */
22 #define BSC_DEL(BASE) __REG32(BASE + 0x0018) /* BSC Master Data Delay */
23 #define BSC_CLKT(BASE) __REG32(BASE + 0x001c) /* BSC Master Clock Stretch Timeout */
A Draspi4.h5 #define __REG32(x) (*((volatile unsigned int *)(x))) macro
137 #define STIMER_CS __REG32(STIMER_BASE + 0x0000)
138 #define STIMER_CLO __REG32(STIMER_BASE + 0x0004)
139 #define STIMER_CHI __REG32(STIMER_BASE + 0x0008)
140 #define STIMER_C0 __REG32(STIMER_BASE + 0x000C)
141 #define STIMER_C1 __REG32(STIMER_BASE + 0x0010)
142 #define STIMER_C2 __REG32(STIMER_BASE + 0x0014)
143 #define STIMER_C3 __REG32(STIMER_BASE + 0x0018)
/bsp/loongson/ls1bdev/drivers/
A Ddisplay_controller.h20 #define DC_FB_CONFIG __REG32(DC_BASE + 0x000)
21 #define DC_FB_BUFFER_ADDR0 __REG32(DC_BASE + 0x020)
22 #define DC_FB_BUFFER_STRIDE __REG32(DC_BASE + 0x040)
23 #define DC_FB_BUFFER_ORIGIN __REG32(DC_BASE + 0x060)
24 #define DC_DITHER_CONFIG __REG32(DC_BASE + 0x120)
25 #define DC_DITHER_TABLE_LOW __REG32(DC_BASE + 0x140)
26 #define DC_DITHER_TABLE_HIGH __REG32(DC_BASE + 0x160)
27 #define DC_PANEL_CONFIG __REG32(DC_BASE + 0x180)
28 #define DC_PANEL_TIMING __REG32(DC_BASE + 0x1A0)
29 #define DC_HDISPLAY __REG32(DC_BASE + 0x1C0)
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/bsp/qemu-vexpress-a9/drivers/
A Ddrv_timer.c27 #define TIMER_LOAD(hw_base) __REG32(hw_base + 0x00)
28 #define TIMER_VALUE(hw_base) __REG32(hw_base + 0x04)
29 #define TIMER_CTRL(hw_base) __REG32(hw_base + 0x08)
39 #define TIMER_INTCLR(hw_base) __REG32(hw_base + 0x0c)
40 #define TIMER_RIS(hw_base) __REG32(hw_base + 0x10)
41 #define TIMER_MIS(hw_base) __REG32(hw_base + 0x14)
42 #define TIMER_BGLOAD(hw_base) __REG32(hw_base + 0x18)
44 #define TIMER_LOAD(hw_base) __REG32(hw_base + 0x00)
45 #define TIMER_VALUE(hw_base) __REG32(hw_base + 0x04)
46 #define TIMER_CTRL(hw_base) __REG32(hw_base + 0x08)
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A Ddrv_uart_v2.c34 #define UART_DR(base) __REG32(base + 0x00)
35 #define UART_FR(base) __REG32(base + 0x18)
36 #define UART_CR(base) __REG32(base + 0x30)
37 #define UART_IMSC(base) __REG32(base + 0x38)
38 #define UART_ICR(base) __REG32(base + 0x44)
39 #define UART_IFLS(base) __REG32(base + 0x34)
40 #define UART_TCR(base) __REG32(base + 0x80)
41 #define UART_ITOP(base) __REG32(base + 0x88)
43 #define UART_LCR_H(base) __REG32(base + 0x2C)
44 #define UART_DMACR(base) __REG32(base + 0x48)
A Ddrv_uart.c31 #define UART_DR(base) __REG32(base + 0x00)
32 #define UART_FR(base) __REG32(base + 0x18)
33 #define UART_CR(base) __REG32(base + 0x30)
34 #define UART_IMSC(base) __REG32(base + 0x38)
35 #define UART_ICR(base) __REG32(base + 0x44)
A Dboard.c40 #define SYS_CTRL __REG32(REALVIEW_SCTL_BASE)
A Drealview.h13 #define __REG32(x) (*((volatile unsigned int *)(x))) macro
/bsp/zynqmp-r5-axu4ev/drivers/
A Ddrv_timer.h10 #define TTC_CLK_CNTRL(hw_base) __REG32(hw_base + 0x00)
18 #define TTC_CNT_CNTRL(hw_base) __REG32(hw_base + 0x0C)
28 #define TTC_COUNT_VALUE(hw_base) __REG32(hw_base + 0x18)
29 #define TTC_INTERVAL_VAL(hw_base) __REG32(hw_base + 0x24)
30 #define TTC_MATCH_0(hw_base) __REG32(hw_base + 0x30)
31 #define TTC_MATCH_1(hw_base) __REG32(hw_base + 0x3C)
32 #define TTC_MATCH_2(hw_base) __REG32(hw_base + 0x48)
34 #define TTC_ISR(hw_base) __REG32(hw_base + 0x54)
42 #define TTC_IER(hw_base) __REG32(hw_base + 0x60)
A Ddrv_uart.h256 !((__REG32((BaseAddress) + UART_SR_OFFSET) & \
273 ((__REG32((BaseAddress) + UART_SR_OFFSET) & \
A Dzynqmp-r5.h16 #define __REG32(x) (*((volatile rt_uint32_t *)(x))) macro
/bsp/raspberry-pi/raspi4-64/drivers/
A Draspi4.h17 #define __REG32(x) (*((volatile unsigned int *)(x))) macro
157 #define STIMER_CS __REG32(stimer_base_addr + 0x0000)
158 #define STIMER_CLO __REG32(stimer_base_addr + 0x0004)
159 #define STIMER_CHI __REG32(stimer_base_addr + 0x0008)
160 #define STIMER_C0 __REG32(stimer_base_addr + 0x000C)
161 #define STIMER_C1 __REG32(stimer_base_addr + 0x0010)
162 #define STIMER_C2 __REG32(stimer_base_addr + 0x0014)
163 #define STIMER_C3 __REG32(stimer_base_addr + 0x0018)
/bsp/qemu-virt64-aarch64/drivers/
A Ddrv_uart.c24 #define UART_DR(base) __REG32(base + 0x00)
25 #define UART_FR(base) __REG32(base + 0x18)
26 #define UART_CR(base) __REG32(base + 0x30)
27 #define UART_IMSC(base) __REG32(base + 0x38)
28 #define UART_ICR(base) __REG32(base + 0x44)
A Dvirt.h21 #define __REG32(x) (*((volatile unsigned int *)(x))) macro
/bsp/raspberry-pi/raspi3-32/driver/
A Dboard.h19 #define __REG32 HWREG32 macro
/bsp/cvitek/cv18xx_aarch64/board/
A Dcv18xx.h21 #define __REG32(x) (*((volatile unsigned int *)(x))) macro
/bsp/zynqmp-a53-dfzu2eg/drivers/
A Dzynqmp.h21 #define __REG32(x) (*((volatile unsigned int *)(x))) macro
/bsp/nuvoton/libraries/ma35/rtt_port/
A Ddrv_common.h29 #define __REG32(x) (*((volatile unsigned int*)((rt_ubase_t)x))) macro
/bsp/nxp/imx/imx6ul/drivers/
A Dimx6ul.h50 #define __REG32(x) (*((volatile unsigned int *)(x))) macro
/bsp/nxp/imx/imx6ull-smart/drivers/
A Dimx6ull.h340 #define __REG32(x) (*((volatile unsigned int *)(x))) macro

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