Searched refs:__RW (Results 1 – 25 of 341) sorted by relevance
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14 __RW uint32_t CTRL; /* 0xC000: Control Register */16 __RW uint32_t INT_EN_REG; /* 0xC008: Interrupt Enable Register */19 __RW uint32_t OP_CTRL0; /* 0xC040: Operation Control Register 0 */20 __RW uint32_t RSA_OP_CTRL; /* 0xC040: RSA Operation Control Register */24 __RW uint32_t OP_CTRL1; /* 0xC044: Operation Control Register 1 */29 __RW uint32_t OP_CTRL2; /* 0xC048: Operation Control Register 2 */55 __RW uint32_t RSA_PUB_KEY; /* 0xC05C: RSA Public Key Register */64 __RW uint32_t RSA_M; /* 0xC064: RSA M Register */69 __RW uint32_t RSA_TM0; /* 0xC068: RSA TM0 Register */74 __RW uint32_t RSA_TM1; /* 0xC06C: RSA TM1 Register */[all …]
14 __RW uint32_t MODE; /* 0x0: mode ctrl */15 __RW uint32_t ADC_EXPECT; /* 0x4: adc expect */16 __RW uint32_t ADC_CHAN; /* 0x8: adc used channel */17 __RW uint32_t ADC_OFFSET; /* 0xC: adc used offset */28 __RW uint32_t COEFF_B0; /* 0x40: zone b0 */29 __RW uint32_t COEFF_B1; /* 0x44: zone b1 */30 __RW uint32_t COEFF_B2; /* 0x48: zone b2 */31 __RW uint32_t COEFF_B3; /* 0x4C: zone b3 */32 __RW uint32_t COEFF_A0; /* 0x50: zone a0 */33 __RW uint32_t COEFF_A1; /* 0x54: zone a1 */[all …]
18 __RW uint32_t VALUE; /* 0x100: GPIO output value */19 __RW uint32_t SET; /* 0x104: GPIO output set */20 __RW uint32_t CLEAR; /* 0x108: GPIO output clear */21 __RW uint32_t TOGGLE; /* 0x10C: GPIO output toggle */24 __RW uint32_t VALUE; /* 0x200: GPIO direction value */25 __RW uint32_t SET; /* 0x204: GPIO direction set */26 __RW uint32_t CLEAR; /* 0x208: GPIO direction clear */27 __RW uint32_t TOGGLE; /* 0x20C: GPIO direction toggle */35 __RW uint32_t SET; /* 0x404: GPIO interrupt enable set */46 __RW uint32_t VALUE; /* 0x600: GPIO interrupt type value */[all …]
13 __RW uint32_t PMIC_GPR00; /* 0x0: Generic control */14 __RW uint32_t PMIC_GPR01; /* 0x4: Generic control */15 __RW uint32_t PMIC_GPR02; /* 0x8: Generic control */16 __RW uint32_t PMIC_GPR03; /* 0xC: Generic control */17 __RW uint32_t PMIC_GPR04; /* 0x10: Generic control */18 __RW uint32_t PMIC_GPR05; /* 0x14: Generic control */19 __RW uint32_t PMIC_GPR06; /* 0x18: Generic control */20 __RW uint32_t PMIC_GPR07; /* 0x1C: Generic control */21 __RW uint32_t PMIC_GPR08; /* 0x20: Generic control */22 __RW uint32_t PMIC_GPR09; /* 0x24: Generic control */[all …]
13 __RW uint32_t CTRL; /* 0x0: Control Register */15 __RW uint32_t STREAMCTRL; /* 0xC: Stream Control Register */16 __RW uint32_t PTACTION; /* 0x10: Pre-trigger Action Register */17 __RW uint32_t STARTADDR; /* 0x14: Start Address Register */18 __RW uint32_t ENDADDR; /* 0x18: End Address Register */25 __RW uint32_t FINALADDR; /* 0x34: Final Address Register */27 __RW uint32_t GRPSELA; /* 0x50: Group Select Register */28 __RW uint32_t GRPENA; /* 0x54: Group Enable Register */33 __RW uint32_t SIGENA; /* 0x98: Signal Enable Register */38 __RW uint32_t NEXTSTATE; /* 0x108: Next State Register */[all …]
13 __RW uint32_t SECOND; /* 0x0: Second counter */15 __RW uint32_t SEC_SNAP; /* 0x8: Second counter snap shot */16 __RW uint32_t SUB_SNAP; /* 0xC: Sub-second counter snap shot */17 __RW uint32_t ALARM0; /* 0x10: RTC alarm0 */18 __RW uint32_t ALARM0_INC; /* 0x14: Alarm0 incremental */19 __RW uint32_t ALARM1; /* 0x18: RTC alarm1 */20 __RW uint32_t ALARM1_INC; /* 0x1C: Alarm1 incremental */21 __RW uint32_t ALARM_FLAG; /* 0x20: RTC alarm flag */22 __RW uint32_t ALARM_EN; /* 0x24: RTC alarm enable */
19 __RW uint32_t VALUE; /* 0x100: GPIO output value */20 __RW uint32_t SET; /* 0x104: GPIO output set */21 __RW uint32_t CLEAR; /* 0x108: GPIO output clear */22 __RW uint32_t TOGGLE; /* 0x10C: GPIO output toggle */26 __RW uint32_t VALUE; /* 0x200: GPIO direction value */27 __RW uint32_t SET; /* 0x204: GPIO direction set */28 __RW uint32_t CLEAR; /* 0x208: GPIO direction clear */29 __RW uint32_t TOGGLE; /* 0x20C: GPIO direction toggle */39 __RW uint32_t SET; /* 0x404: GPIO interrupt enable set */52 __RW uint32_t VALUE; /* 0x600: GPIO interrupt type value */[all …]
13 __RW uint32_t CR; /* 0x0: Control Register */14 __RW uint32_t STA; /* 0x4: Status Register */15 __RW uint32_t INT_EN; /* 0x8: Interrupt Enable Register */16 __RW uint32_t SYSCLK_FREQ; /* 0xC: System Clock Frequency Register */17 __RW uint32_t SYSCLK_PERIOD; /* 0x10: System Clock Period Register */18 __RW uint32_t OOSYNC_THETA_THR; /* 0x14: Position Out-Of-Sync Threshold Regster */19 __RW uint32_t DISCRETECFG0; /* 0x18: Discrete Mode Configuration 0 Register */20 __RW uint32_t DISCRETECFG1; /* 0x1C: Discrete Mode Configuration 1 Register */60 __RW uint32_t BR_CTRL; /* 0x100: Prediction Control Register */61 __RW uint32_t BR_TIMEOFF; /* 0x104: Prediction Timing Offset Register */[all …]
13 __RW uint32_t CTRL; /* 0x0: */14 __RW uint32_t STATUS; /* 0x4: */15 __RW uint32_t INT_EN; /* 0x8: */17 __RW uint32_t OP_CTRL; /* 0x20: */18 __RW uint32_t OP_CMD; /* 0x24: */20 __RW uint32_t OP_REG0; /* 0x28: */21 __RW uint32_t OP_FIR_MISC; /* 0x28: */22 __RW uint32_t OP_FFT_MISC; /* 0x28: */25 __RW uint32_t OP_REG1; /* 0x2C: */26 __RW uint32_t OP_FIR_MISC1; /* 0x2C: */[all …]
13 __RW uint32_t CLANE_PARA0; /* 0x0: timer counter about clock lane parameter */14 __RW uint32_t CLANE_PARA1; /* 0x4: timer counter about clock lane parameter */15 __RW uint32_t CLANE_PARA2; /* 0x8: timer counter about clock lane parameter */34 __RW uint32_t COMMON_PARA0; /* 0x54: timing parameter for all lanes */35 __RW uint32_t CTRL_PARA0; /* 0x58: dphy control parameter */36 __RW uint32_t PLL_CTRL_PARA0; /* 0x5C: dphy pll control parameter */39 __RW uint32_t TRIM_PARA; /* 0x68: dphy trimming parameter */40 __RW uint32_t TEST_PARA0; /* 0x6C: dphy test control parameter */41 __RW uint32_t TEST_PARA1; /* 0x70: dphy bist test control parameter */42 __RW uint32_t MISC_PARA; /* 0x74: dphy control parameter */[all …]
13 __RW uint32_t XTAL; /* 0x0: OSC configuration */16 __RW uint32_t MFI; /* 0x80: PLL0 multiple register */17 __RW uint32_t MFN; /* 0x84: PLL0 fraction numerator register */18 __RW uint32_t MFD; /* 0x88: PLL0 fraction demoninator register */19 __RW uint32_t SS_STEP; /* 0x8C: PLL0 spread spectrum step register */20 __RW uint32_t SS_STOP; /* 0x90: PLL0 spread spectrum stop register */21 __RW uint32_t CONFIG; /* 0x94: PLL0 confguration register */22 __RW uint32_t LOCKTIME; /* 0x98: PLL0 lock time register */23 __RW uint32_t STEPTIME; /* 0x9C: PLL0 step time register */24 __RW uint32_t ADVANCED; /* 0xA0: PLL0 advance configuration register */[all …]
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