| /bsp/synwit/libraries/SWM341_CSL/CMSIS/CoreSupport/ |
| A D | cachel1_armv7.h | 45 #ifndef __SCB_DCACHE_LINE_SIZE
46 #define __SCB_DCACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). … macro
332 int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); in SCB_InvalidateDCache_by_Addr()
339 op_addr += __SCB_DCACHE_LINE_SIZE; in SCB_InvalidateDCache_by_Addr()
340 op_size -= __SCB_DCACHE_LINE_SIZE; in SCB_InvalidateDCache_by_Addr()
362 int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); in SCB_CleanDCache_by_Addr()
369 op_addr += __SCB_DCACHE_LINE_SIZE; in SCB_CleanDCache_by_Addr()
370 op_size -= __SCB_DCACHE_LINE_SIZE; in SCB_CleanDCache_by_Addr()
392 int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); in SCB_CleanInvalidateDCache_by_Addr()
399 op_addr += __SCB_DCACHE_LINE_SIZE; in SCB_CleanInvalidateDCache_by_Addr()
[all …]
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| /bsp/airm2m/air32f103/libraries/CMSIS/Include/ |
| A D | cachel1_armv7.h | 45 #ifndef __SCB_DCACHE_LINE_SIZE
46 #define __SCB_DCACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). … macro
332 int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); in SCB_InvalidateDCache_by_Addr()
339 op_addr += __SCB_DCACHE_LINE_SIZE; in SCB_InvalidateDCache_by_Addr()
340 op_size -= __SCB_DCACHE_LINE_SIZE; in SCB_InvalidateDCache_by_Addr()
362 int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); in SCB_CleanDCache_by_Addr()
369 op_addr += __SCB_DCACHE_LINE_SIZE; in SCB_CleanDCache_by_Addr()
370 op_size -= __SCB_DCACHE_LINE_SIZE; in SCB_CleanDCache_by_Addr()
392 int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); in SCB_CleanInvalidateDCache_by_Addr()
399 op_addr += __SCB_DCACHE_LINE_SIZE; in SCB_CleanInvalidateDCache_by_Addr()
[all …]
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| /bsp/rockchip/common/rk_hal/lib/CMSIS/Core/Include/ |
| A D | cachel1_armv7.h | 45 #ifndef __SCB_DCACHE_LINE_SIZE
46 #define __SCB_DCACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). … macro
332 int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); in SCB_InvalidateDCache_by_Addr()
339 op_addr += __SCB_DCACHE_LINE_SIZE; in SCB_InvalidateDCache_by_Addr()
340 op_size -= __SCB_DCACHE_LINE_SIZE; in SCB_InvalidateDCache_by_Addr()
362 int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); in SCB_CleanDCache_by_Addr()
369 op_addr += __SCB_DCACHE_LINE_SIZE; in SCB_CleanDCache_by_Addr()
370 op_size -= __SCB_DCACHE_LINE_SIZE; in SCB_CleanDCache_by_Addr()
392 int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); in SCB_CleanInvalidateDCache_by_Addr()
399 op_addr += __SCB_DCACHE_LINE_SIZE; in SCB_CleanInvalidateDCache_by_Addr()
[all …]
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| /bsp/tae32f5300/Libraries/CMSIS/Include/ |
| A D | cachel1_armv7.h | 45 #ifndef __SCB_DCACHE_LINE_SIZE
46 #define __SCB_DCACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). … macro
332 int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); in SCB_InvalidateDCache_by_Addr()
339 op_addr += __SCB_DCACHE_LINE_SIZE; in SCB_InvalidateDCache_by_Addr()
340 op_size -= __SCB_DCACHE_LINE_SIZE; in SCB_InvalidateDCache_by_Addr()
362 int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); in SCB_CleanDCache_by_Addr()
369 op_addr += __SCB_DCACHE_LINE_SIZE; in SCB_CleanDCache_by_Addr()
370 op_size -= __SCB_DCACHE_LINE_SIZE; in SCB_CleanDCache_by_Addr()
392 int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); in SCB_CleanInvalidateDCache_by_Addr()
399 op_addr += __SCB_DCACHE_LINE_SIZE; in SCB_CleanInvalidateDCache_by_Addr()
[all …]
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| /bsp/renesas/ra8m1-ek/ra/arm/CMSIS_5/CMSIS/Core/Include/ |
| A D | cachel1_armv7.h | 45 #ifndef __SCB_DCACHE_LINE_SIZE
46 #define __SCB_DCACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). … macro
332 int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); in SCB_InvalidateDCache_by_Addr()
339 op_addr += __SCB_DCACHE_LINE_SIZE; in SCB_InvalidateDCache_by_Addr()
340 op_size -= __SCB_DCACHE_LINE_SIZE; in SCB_InvalidateDCache_by_Addr()
362 int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); in SCB_CleanDCache_by_Addr()
369 op_addr += __SCB_DCACHE_LINE_SIZE; in SCB_CleanDCache_by_Addr()
370 op_size -= __SCB_DCACHE_LINE_SIZE; in SCB_CleanDCache_by_Addr()
392 int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); in SCB_CleanInvalidateDCache_by_Addr()
399 op_addr += __SCB_DCACHE_LINE_SIZE; in SCB_CleanInvalidateDCache_by_Addr()
[all …]
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| /bsp/renesas/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/ |
| A D | cachel1_armv7.h | 45 #ifndef __SCB_DCACHE_LINE_SIZE
46 #define __SCB_DCACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). … macro
332 int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); in SCB_InvalidateDCache_by_Addr()
339 op_addr += __SCB_DCACHE_LINE_SIZE; in SCB_InvalidateDCache_by_Addr()
340 op_size -= __SCB_DCACHE_LINE_SIZE; in SCB_InvalidateDCache_by_Addr()
362 int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); in SCB_CleanDCache_by_Addr()
369 op_addr += __SCB_DCACHE_LINE_SIZE; in SCB_CleanDCache_by_Addr()
370 op_size -= __SCB_DCACHE_LINE_SIZE; in SCB_CleanDCache_by_Addr()
392 int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); in SCB_CleanInvalidateDCache_by_Addr()
399 op_addr += __SCB_DCACHE_LINE_SIZE; in SCB_CleanInvalidateDCache_by_Addr()
[all …]
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| /bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/ |
| A D | cachel1_armv7.h | 45 #ifndef __SCB_DCACHE_LINE_SIZE
46 #define __SCB_DCACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). … macro
332 int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); in SCB_InvalidateDCache_by_Addr()
339 op_addr += __SCB_DCACHE_LINE_SIZE; in SCB_InvalidateDCache_by_Addr()
340 op_size -= __SCB_DCACHE_LINE_SIZE; in SCB_InvalidateDCache_by_Addr()
362 int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); in SCB_CleanDCache_by_Addr()
369 op_addr += __SCB_DCACHE_LINE_SIZE; in SCB_CleanDCache_by_Addr()
370 op_size -= __SCB_DCACHE_LINE_SIZE; in SCB_CleanDCache_by_Addr()
392 int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); in SCB_CleanInvalidateDCache_by_Addr()
399 op_addr += __SCB_DCACHE_LINE_SIZE; in SCB_CleanInvalidateDCache_by_Addr()
[all …]
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| /bsp/renesas/ra8d1-vision-board/ra/arm/CMSIS_5/CMSIS/Core/Include/ |
| A D | cachel1_armv7.h | 45 #ifndef __SCB_DCACHE_LINE_SIZE
46 #define __SCB_DCACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). … macro
332 int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); in SCB_InvalidateDCache_by_Addr()
339 op_addr += __SCB_DCACHE_LINE_SIZE; in SCB_InvalidateDCache_by_Addr()
340 op_size -= __SCB_DCACHE_LINE_SIZE; in SCB_InvalidateDCache_by_Addr()
362 int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); in SCB_CleanDCache_by_Addr()
369 op_addr += __SCB_DCACHE_LINE_SIZE; in SCB_CleanDCache_by_Addr()
370 op_size -= __SCB_DCACHE_LINE_SIZE; in SCB_CleanDCache_by_Addr()
392 int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); in SCB_CleanInvalidateDCache_by_Addr()
399 op_addr += __SCB_DCACHE_LINE_SIZE; in SCB_CleanInvalidateDCache_by_Addr()
[all …]
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| A D | core_starmc1.h | 3071 #define __SCB_DCACHE_LINE_SIZE 32U /*!< STAR-MC1 cache line size is fixed to 32 bytes (8 words). S… macro
3353 int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); in SCB_InvalidateDCache_by_Addr()
3360 op_addr += __SCB_DCACHE_LINE_SIZE; in SCB_InvalidateDCache_by_Addr()
3361 op_size -= __SCB_DCACHE_LINE_SIZE; in SCB_InvalidateDCache_by_Addr()
3383 int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); in SCB_CleanDCache_by_Addr()
3390 op_addr += __SCB_DCACHE_LINE_SIZE; in SCB_CleanDCache_by_Addr()
3391 op_size -= __SCB_DCACHE_LINE_SIZE; in SCB_CleanDCache_by_Addr()
3413 int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); in SCB_CleanInvalidateDCache_by_Addr()
3420 op_addr += __SCB_DCACHE_LINE_SIZE; in SCB_CleanInvalidateDCache_by_Addr()
3421 op_size -= __SCB_DCACHE_LINE_SIZE; in SCB_CleanInvalidateDCache_by_Addr()
|
| /bsp/renesas/ra6m4-iot/ra/arm/CMSIS_5/CMSIS/Core/Include/ |
| A D | cachel1_armv7.h | 45 #ifndef __SCB_DCACHE_LINE_SIZE
46 #define __SCB_DCACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). … macro
332 int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); in SCB_InvalidateDCache_by_Addr()
339 op_addr += __SCB_DCACHE_LINE_SIZE; in SCB_InvalidateDCache_by_Addr()
340 op_size -= __SCB_DCACHE_LINE_SIZE; in SCB_InvalidateDCache_by_Addr()
362 int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); in SCB_CleanDCache_by_Addr()
369 op_addr += __SCB_DCACHE_LINE_SIZE; in SCB_CleanDCache_by_Addr()
370 op_size -= __SCB_DCACHE_LINE_SIZE; in SCB_CleanDCache_by_Addr()
392 int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); in SCB_CleanInvalidateDCache_by_Addr()
399 op_addr += __SCB_DCACHE_LINE_SIZE; in SCB_CleanInvalidateDCache_by_Addr()
[all …]
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| /bsp/renesas/ra6m3-hmi-board/ra/arm/CMSIS_5/CMSIS/Core/Include/ |
| A D | cachel1_armv7.h | 45 #ifndef __SCB_DCACHE_LINE_SIZE
46 #define __SCB_DCACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). … macro
332 int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); in SCB_InvalidateDCache_by_Addr()
339 op_addr += __SCB_DCACHE_LINE_SIZE; in SCB_InvalidateDCache_by_Addr()
340 op_size -= __SCB_DCACHE_LINE_SIZE; in SCB_InvalidateDCache_by_Addr()
362 int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); in SCB_CleanDCache_by_Addr()
369 op_addr += __SCB_DCACHE_LINE_SIZE; in SCB_CleanDCache_by_Addr()
370 op_size -= __SCB_DCACHE_LINE_SIZE; in SCB_CleanDCache_by_Addr()
392 int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); in SCB_CleanInvalidateDCache_by_Addr()
399 op_addr += __SCB_DCACHE_LINE_SIZE; in SCB_CleanInvalidateDCache_by_Addr()
[all …]
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| /bsp/renesas/ra4m2-eco/ra/arm/CMSIS_5/CMSIS/Core/Include/ |
| A D | cachel1_armv7.h | 45 #ifndef __SCB_DCACHE_LINE_SIZE
46 #define __SCB_DCACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). … macro
332 int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); in SCB_InvalidateDCache_by_Addr()
339 op_addr += __SCB_DCACHE_LINE_SIZE; in SCB_InvalidateDCache_by_Addr()
340 op_size -= __SCB_DCACHE_LINE_SIZE; in SCB_InvalidateDCache_by_Addr()
362 int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); in SCB_CleanDCache_by_Addr()
369 op_addr += __SCB_DCACHE_LINE_SIZE; in SCB_CleanDCache_by_Addr()
370 op_size -= __SCB_DCACHE_LINE_SIZE; in SCB_CleanDCache_by_Addr()
392 int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); in SCB_CleanInvalidateDCache_by_Addr()
399 op_addr += __SCB_DCACHE_LINE_SIZE; in SCB_CleanInvalidateDCache_by_Addr()
[all …]
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| /bsp/renesas/ebf_qi_min_6m5/ra/arm/CMSIS_5/CMSIS/Core/Include/ |
| A D | cachel1_armv7.h | 45 #ifndef __SCB_DCACHE_LINE_SIZE
46 #define __SCB_DCACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). … macro
332 int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); in SCB_InvalidateDCache_by_Addr()
339 op_addr += __SCB_DCACHE_LINE_SIZE; in SCB_InvalidateDCache_by_Addr()
340 op_size -= __SCB_DCACHE_LINE_SIZE; in SCB_InvalidateDCache_by_Addr()
362 int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); in SCB_CleanDCache_by_Addr()
369 op_addr += __SCB_DCACHE_LINE_SIZE; in SCB_CleanDCache_by_Addr()
370 op_size -= __SCB_DCACHE_LINE_SIZE; in SCB_CleanDCache_by_Addr()
392 int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); in SCB_CleanInvalidateDCache_by_Addr()
399 op_addr += __SCB_DCACHE_LINE_SIZE; in SCB_CleanInvalidateDCache_by_Addr()
[all …]
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| /bsp/renesas/ra2l1-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/ |
| A D | cachel1_armv7.h | 45 #ifndef __SCB_DCACHE_LINE_SIZE
46 #define __SCB_DCACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). … macro
332 int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); in SCB_InvalidateDCache_by_Addr()
339 op_addr += __SCB_DCACHE_LINE_SIZE; in SCB_InvalidateDCache_by_Addr()
340 op_size -= __SCB_DCACHE_LINE_SIZE; in SCB_InvalidateDCache_by_Addr()
362 int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); in SCB_CleanDCache_by_Addr()
369 op_addr += __SCB_DCACHE_LINE_SIZE; in SCB_CleanDCache_by_Addr()
370 op_size -= __SCB_DCACHE_LINE_SIZE; in SCB_CleanDCache_by_Addr()
392 int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); in SCB_CleanInvalidateDCache_by_Addr()
399 op_addr += __SCB_DCACHE_LINE_SIZE; in SCB_CleanInvalidateDCache_by_Addr()
[all …]
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| /bsp/renesas/ra6m3-ek/ra/arm/CMSIS_5/CMSIS/Core/Include/ |
| A D | cachel1_armv7.h | 45 #ifndef __SCB_DCACHE_LINE_SIZE
46 #define __SCB_DCACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). … macro
332 int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); in SCB_InvalidateDCache_by_Addr()
339 op_addr += __SCB_DCACHE_LINE_SIZE; in SCB_InvalidateDCache_by_Addr()
340 op_size -= __SCB_DCACHE_LINE_SIZE; in SCB_InvalidateDCache_by_Addr()
362 int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); in SCB_CleanDCache_by_Addr()
369 op_addr += __SCB_DCACHE_LINE_SIZE; in SCB_CleanDCache_by_Addr()
370 op_size -= __SCB_DCACHE_LINE_SIZE; in SCB_CleanDCache_by_Addr()
392 int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); in SCB_CleanInvalidateDCache_by_Addr()
399 op_addr += __SCB_DCACHE_LINE_SIZE; in SCB_CleanInvalidateDCache_by_Addr()
[all …]
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| /bsp/renesas/ra8d1-ek/ra/arm/CMSIS_5/CMSIS/Core/Include/ |
| A D | cachel1_armv7.h | 45 #ifndef __SCB_DCACHE_LINE_SIZE
46 #define __SCB_DCACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). … macro
332 int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); in SCB_InvalidateDCache_by_Addr()
339 op_addr += __SCB_DCACHE_LINE_SIZE; in SCB_InvalidateDCache_by_Addr()
340 op_size -= __SCB_DCACHE_LINE_SIZE; in SCB_InvalidateDCache_by_Addr()
362 int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); in SCB_CleanDCache_by_Addr()
369 op_addr += __SCB_DCACHE_LINE_SIZE; in SCB_CleanDCache_by_Addr()
370 op_size -= __SCB_DCACHE_LINE_SIZE; in SCB_CleanDCache_by_Addr()
392 int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); in SCB_CleanInvalidateDCache_by_Addr()
399 op_addr += __SCB_DCACHE_LINE_SIZE; in SCB_CleanInvalidateDCache_by_Addr()
[all …]
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| /bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/ |
| A D | cachel1_armv7.h | 45 #ifndef __SCB_DCACHE_LINE_SIZE
46 #define __SCB_DCACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). … macro
332 int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); in SCB_InvalidateDCache_by_Addr()
339 op_addr += __SCB_DCACHE_LINE_SIZE; in SCB_InvalidateDCache_by_Addr()
340 op_size -= __SCB_DCACHE_LINE_SIZE; in SCB_InvalidateDCache_by_Addr()
362 int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); in SCB_CleanDCache_by_Addr()
369 op_addr += __SCB_DCACHE_LINE_SIZE; in SCB_CleanDCache_by_Addr()
370 op_size -= __SCB_DCACHE_LINE_SIZE; in SCB_CleanDCache_by_Addr()
392 int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); in SCB_CleanInvalidateDCache_by_Addr()
399 op_addr += __SCB_DCACHE_LINE_SIZE; in SCB_CleanInvalidateDCache_by_Addr()
[all …]
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| /bsp/renesas/ra6e2-fpb/ra/arm/CMSIS_6/CMSIS/Core/Include/m-profile/ |
| A D | armv7m_cachel1.h | 43 #ifndef __SCB_DCACHE_LINE_SIZE
188 __ALIGNED(__SCB_DCACHE_LINE_SIZE) in SCB_DisableDCache()
360 int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); in SCB_InvalidateDCache_by_Addr()
367 op_addr += __SCB_DCACHE_LINE_SIZE; in SCB_InvalidateDCache_by_Addr()
368 op_size -= __SCB_DCACHE_LINE_SIZE; in SCB_InvalidateDCache_by_Addr()
390 int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); in SCB_CleanDCache_by_Addr()
397 op_addr += __SCB_DCACHE_LINE_SIZE; in SCB_CleanDCache_by_Addr()
398 op_size -= __SCB_DCACHE_LINE_SIZE; in SCB_CleanDCache_by_Addr()
420 int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); in SCB_CleanInvalidateDCache_by_Addr()
427 op_addr += __SCB_DCACHE_LINE_SIZE; in SCB_CleanInvalidateDCache_by_Addr()
[all …]
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| /bsp/renesas/ra4e2-eco/ra/arm/CMSIS_6/CMSIS/Core/Include/m-profile/ |
| A D | armv7m_cachel1.h | 43 #ifndef __SCB_DCACHE_LINE_SIZE
189 __ALIGNED(__SCB_DCACHE_LINE_SIZE) in SCB_DisableDCache()
362 int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); in SCB_InvalidateDCache_by_Addr()
369 op_addr += __SCB_DCACHE_LINE_SIZE; in SCB_InvalidateDCache_by_Addr()
370 op_size -= __SCB_DCACHE_LINE_SIZE; in SCB_InvalidateDCache_by_Addr()
393 int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); in SCB_CleanDCache_by_Addr()
400 op_addr += __SCB_DCACHE_LINE_SIZE; in SCB_CleanDCache_by_Addr()
401 op_size -= __SCB_DCACHE_LINE_SIZE; in SCB_CleanDCache_by_Addr()
424 int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); in SCB_CleanInvalidateDCache_by_Addr()
431 op_addr += __SCB_DCACHE_LINE_SIZE; in SCB_CleanInvalidateDCache_by_Addr()
[all …]
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| /bsp/at32/libraries/CMSIS/include/ |
| A D | cachel1_armv7.h | 45 #ifndef __SCB_DCACHE_LINE_SIZE
190 __ALIGNED(__SCB_DCACHE_LINE_SIZE) in SCB_DisableDCache()
362 int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); in SCB_InvalidateDCache_by_Addr()
369 op_addr += __SCB_DCACHE_LINE_SIZE; in SCB_InvalidateDCache_by_Addr()
370 op_size -= __SCB_DCACHE_LINE_SIZE; in SCB_InvalidateDCache_by_Addr()
392 int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); in SCB_CleanDCache_by_Addr()
399 op_addr += __SCB_DCACHE_LINE_SIZE; in SCB_CleanDCache_by_Addr()
400 op_size -= __SCB_DCACHE_LINE_SIZE; in SCB_CleanDCache_by_Addr()
422 int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); in SCB_CleanInvalidateDCache_by_Addr()
429 op_addr += __SCB_DCACHE_LINE_SIZE; in SCB_CleanInvalidateDCache_by_Addr()
[all …]
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| /bsp/msp432e401y-LaunchPad/libraries/Drivers/CMSIS/Include/ |
| A D | core_cm7.h | 2231 #define __SCB_DCACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). … macro
2503 int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); in SCB_InvalidateDCache_by_Addr()
2511 op_addr += __SCB_DCACHE_LINE_SIZE; in SCB_InvalidateDCache_by_Addr()
2512 op_size -= __SCB_DCACHE_LINE_SIZE; in SCB_InvalidateDCache_by_Addr()
2536 int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); in SCB_CleanDCache_by_Addr()
2544 op_addr += __SCB_DCACHE_LINE_SIZE; in SCB_CleanDCache_by_Addr()
2545 op_size -= __SCB_DCACHE_LINE_SIZE; in SCB_CleanDCache_by_Addr()
2569 int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); in SCB_CleanInvalidateDCache_by_Addr()
2577 op_addr += __SCB_DCACHE_LINE_SIZE; in SCB_CleanInvalidateDCache_by_Addr()
2578 op_size -= __SCB_DCACHE_LINE_SIZE; in SCB_CleanInvalidateDCache_by_Addr()
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| /bsp/hc32l196/Libraries/CMSIS/Include/ |
| A D | core_cm7.h | 2234 #define __SCB_DCACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). … macro
2516 int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); in SCB_InvalidateDCache_by_Addr()
2523 op_addr += __SCB_DCACHE_LINE_SIZE; in SCB_InvalidateDCache_by_Addr()
2524 op_size -= __SCB_DCACHE_LINE_SIZE; in SCB_InvalidateDCache_by_Addr()
2546 int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); in SCB_CleanDCache_by_Addr()
2553 op_addr += __SCB_DCACHE_LINE_SIZE; in SCB_CleanDCache_by_Addr()
2554 op_size -= __SCB_DCACHE_LINE_SIZE; in SCB_CleanDCache_by_Addr()
2576 int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); in SCB_CleanInvalidateDCache_by_Addr()
2583 op_addr += __SCB_DCACHE_LINE_SIZE; in SCB_CleanInvalidateDCache_by_Addr()
2584 op_size -= __SCB_DCACHE_LINE_SIZE; in SCB_CleanInvalidateDCache_by_Addr()
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| /bsp/hc32l136/Libraries/CMSIS/Include/ |
| A D | core_cm7.h | 2234 #define __SCB_DCACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). … macro
2516 int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); in SCB_InvalidateDCache_by_Addr()
2523 op_addr += __SCB_DCACHE_LINE_SIZE; in SCB_InvalidateDCache_by_Addr()
2524 op_size -= __SCB_DCACHE_LINE_SIZE; in SCB_InvalidateDCache_by_Addr()
2546 int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); in SCB_CleanDCache_by_Addr()
2553 op_addr += __SCB_DCACHE_LINE_SIZE; in SCB_CleanDCache_by_Addr()
2554 op_size -= __SCB_DCACHE_LINE_SIZE; in SCB_CleanDCache_by_Addr()
2576 int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); in SCB_CleanInvalidateDCache_by_Addr()
2583 op_addr += __SCB_DCACHE_LINE_SIZE; in SCB_CleanInvalidateDCache_by_Addr()
2584 op_size -= __SCB_DCACHE_LINE_SIZE; in SCB_CleanInvalidateDCache_by_Addr()
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| /bsp/mm32/libraries/MM32F3270_HAL/CMSIS/Include/ |
| A D | core_cm7.h | 2234 #define __SCB_DCACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). … macro
2516 int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); in SCB_InvalidateDCache_by_Addr()
2523 op_addr += __SCB_DCACHE_LINE_SIZE; in SCB_InvalidateDCache_by_Addr()
2524 op_size -= __SCB_DCACHE_LINE_SIZE; in SCB_InvalidateDCache_by_Addr()
2546 int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); in SCB_CleanDCache_by_Addr()
2553 op_addr += __SCB_DCACHE_LINE_SIZE; in SCB_CleanDCache_by_Addr()
2554 op_size -= __SCB_DCACHE_LINE_SIZE; in SCB_CleanDCache_by_Addr()
2576 int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); in SCB_CleanInvalidateDCache_by_Addr()
2583 op_addr += __SCB_DCACHE_LINE_SIZE; in SCB_CleanInvalidateDCache_by_Addr()
2584 op_size -= __SCB_DCACHE_LINE_SIZE; in SCB_CleanInvalidateDCache_by_Addr()
|
| /bsp/nrf5x/libraries/cmsis/include/ |
| A D | core_cm7.h | 2234 #define __SCB_DCACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). … macro
2516 int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); in SCB_InvalidateDCache_by_Addr()
2523 op_addr += __SCB_DCACHE_LINE_SIZE; in SCB_InvalidateDCache_by_Addr()
2524 op_size -= __SCB_DCACHE_LINE_SIZE; in SCB_InvalidateDCache_by_Addr()
2546 int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); in SCB_CleanDCache_by_Addr()
2553 op_addr += __SCB_DCACHE_LINE_SIZE; in SCB_CleanDCache_by_Addr()
2554 op_size -= __SCB_DCACHE_LINE_SIZE; in SCB_CleanDCache_by_Addr()
2576 int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); in SCB_CleanInvalidateDCache_by_Addr()
2583 op_addr += __SCB_DCACHE_LINE_SIZE; in SCB_CleanInvalidateDCache_by_Addr()
2584 op_size -= __SCB_DCACHE_LINE_SIZE; in SCB_CleanInvalidateDCache_by_Addr()
|