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Searched refs:__SCB_ICACHE_LINE_SIZE (Results 1 – 25 of 35) sorted by relevance

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/bsp/synwit/libraries/SWM341_CSL/CMSIS/CoreSupport/
A Dcachel1_armv7.h49 #ifndef __SCB_ICACHE_LINE_SIZE
50 #define __SCB_ICACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). … macro
119 int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U)); in SCB_InvalidateICache_by_Addr()
126 op_addr += __SCB_ICACHE_LINE_SIZE; in SCB_InvalidateICache_by_Addr()
127 op_size -= __SCB_ICACHE_LINE_SIZE; in SCB_InvalidateICache_by_Addr()
/bsp/airm2m/air32f103/libraries/CMSIS/Include/
A Dcachel1_armv7.h49 #ifndef __SCB_ICACHE_LINE_SIZE
50 #define __SCB_ICACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). … macro
119 int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U)); in SCB_InvalidateICache_by_Addr()
126 op_addr += __SCB_ICACHE_LINE_SIZE; in SCB_InvalidateICache_by_Addr()
127 op_size -= __SCB_ICACHE_LINE_SIZE; in SCB_InvalidateICache_by_Addr()
/bsp/rockchip/common/rk_hal/lib/CMSIS/Core/Include/
A Dcachel1_armv7.h49 #ifndef __SCB_ICACHE_LINE_SIZE
50 #define __SCB_ICACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). … macro
119 int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U)); in SCB_InvalidateICache_by_Addr()
126 op_addr += __SCB_ICACHE_LINE_SIZE; in SCB_InvalidateICache_by_Addr()
127 op_size -= __SCB_ICACHE_LINE_SIZE; in SCB_InvalidateICache_by_Addr()
/bsp/tae32f5300/Libraries/CMSIS/Include/
A Dcachel1_armv7.h49 #ifndef __SCB_ICACHE_LINE_SIZE
50 #define __SCB_ICACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). … macro
119 int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U)); in SCB_InvalidateICache_by_Addr()
126 op_addr += __SCB_ICACHE_LINE_SIZE; in SCB_InvalidateICache_by_Addr()
127 op_size -= __SCB_ICACHE_LINE_SIZE; in SCB_InvalidateICache_by_Addr()
/bsp/renesas/ra8m1-ek/ra/arm/CMSIS_5/CMSIS/Core/Include/
A Dcachel1_armv7.h49 #ifndef __SCB_ICACHE_LINE_SIZE
50 #define __SCB_ICACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). … macro
119 int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U)); in SCB_InvalidateICache_by_Addr()
126 op_addr += __SCB_ICACHE_LINE_SIZE; in SCB_InvalidateICache_by_Addr()
127 op_size -= __SCB_ICACHE_LINE_SIZE; in SCB_InvalidateICache_by_Addr()
A Dcore_starmc1.h3072 #define __SCB_ICACHE_LINE_SIZE 32U /*!< STAR-MC1 cache line size is fixed to 32 bytes (8 words). S… macro
3140 int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U)); in SCB_InvalidateICache_by_Addr()
3147 op_addr += __SCB_ICACHE_LINE_SIZE; in SCB_InvalidateICache_by_Addr()
3148 op_size -= __SCB_ICACHE_LINE_SIZE; in SCB_InvalidateICache_by_Addr()
/bsp/renesas/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/
A Dcachel1_armv7.h49 #ifndef __SCB_ICACHE_LINE_SIZE
50 #define __SCB_ICACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). … macro
119 int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U)); in SCB_InvalidateICache_by_Addr()
126 op_addr += __SCB_ICACHE_LINE_SIZE; in SCB_InvalidateICache_by_Addr()
127 op_size -= __SCB_ICACHE_LINE_SIZE; in SCB_InvalidateICache_by_Addr()
/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/
A Dcachel1_armv7.h49 #ifndef __SCB_ICACHE_LINE_SIZE
50 #define __SCB_ICACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). … macro
119 int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U)); in SCB_InvalidateICache_by_Addr()
126 op_addr += __SCB_ICACHE_LINE_SIZE; in SCB_InvalidateICache_by_Addr()
127 op_size -= __SCB_ICACHE_LINE_SIZE; in SCB_InvalidateICache_by_Addr()
/bsp/renesas/ra8d1-vision-board/ra/arm/CMSIS_5/CMSIS/Core/Include/
A Dcachel1_armv7.h49 #ifndef __SCB_ICACHE_LINE_SIZE
50 #define __SCB_ICACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). … macro
119 int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U)); in SCB_InvalidateICache_by_Addr()
126 op_addr += __SCB_ICACHE_LINE_SIZE; in SCB_InvalidateICache_by_Addr()
127 op_size -= __SCB_ICACHE_LINE_SIZE; in SCB_InvalidateICache_by_Addr()
A Dcore_starmc1.h3072 #define __SCB_ICACHE_LINE_SIZE 32U /*!< STAR-MC1 cache line size is fixed to 32 bytes (8 words). S… macro
3140 int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U)); in SCB_InvalidateICache_by_Addr()
3147 op_addr += __SCB_ICACHE_LINE_SIZE; in SCB_InvalidateICache_by_Addr()
3148 op_size -= __SCB_ICACHE_LINE_SIZE; in SCB_InvalidateICache_by_Addr()
/bsp/renesas/ra6m4-iot/ra/arm/CMSIS_5/CMSIS/Core/Include/
A Dcachel1_armv7.h49 #ifndef __SCB_ICACHE_LINE_SIZE
50 #define __SCB_ICACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). … macro
119 int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U)); in SCB_InvalidateICache_by_Addr()
126 op_addr += __SCB_ICACHE_LINE_SIZE; in SCB_InvalidateICache_by_Addr()
127 op_size -= __SCB_ICACHE_LINE_SIZE; in SCB_InvalidateICache_by_Addr()
/bsp/renesas/ra6m3-hmi-board/ra/arm/CMSIS_5/CMSIS/Core/Include/
A Dcachel1_armv7.h49 #ifndef __SCB_ICACHE_LINE_SIZE
50 #define __SCB_ICACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). … macro
119 int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U)); in SCB_InvalidateICache_by_Addr()
126 op_addr += __SCB_ICACHE_LINE_SIZE; in SCB_InvalidateICache_by_Addr()
127 op_size -= __SCB_ICACHE_LINE_SIZE; in SCB_InvalidateICache_by_Addr()
/bsp/renesas/ra4m2-eco/ra/arm/CMSIS_5/CMSIS/Core/Include/
A Dcachel1_armv7.h49 #ifndef __SCB_ICACHE_LINE_SIZE
50 #define __SCB_ICACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). … macro
119 int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U)); in SCB_InvalidateICache_by_Addr()
126 op_addr += __SCB_ICACHE_LINE_SIZE; in SCB_InvalidateICache_by_Addr()
127 op_size -= __SCB_ICACHE_LINE_SIZE; in SCB_InvalidateICache_by_Addr()
/bsp/renesas/ebf_qi_min_6m5/ra/arm/CMSIS_5/CMSIS/Core/Include/
A Dcachel1_armv7.h49 #ifndef __SCB_ICACHE_LINE_SIZE
50 #define __SCB_ICACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). … macro
119 int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U)); in SCB_InvalidateICache_by_Addr()
126 op_addr += __SCB_ICACHE_LINE_SIZE; in SCB_InvalidateICache_by_Addr()
127 op_size -= __SCB_ICACHE_LINE_SIZE; in SCB_InvalidateICache_by_Addr()
/bsp/renesas/ra2l1-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/
A Dcachel1_armv7.h49 #ifndef __SCB_ICACHE_LINE_SIZE
50 #define __SCB_ICACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). … macro
119 int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U)); in SCB_InvalidateICache_by_Addr()
126 op_addr += __SCB_ICACHE_LINE_SIZE; in SCB_InvalidateICache_by_Addr()
127 op_size -= __SCB_ICACHE_LINE_SIZE; in SCB_InvalidateICache_by_Addr()
/bsp/renesas/ra6m3-ek/ra/arm/CMSIS_5/CMSIS/Core/Include/
A Dcachel1_armv7.h49 #ifndef __SCB_ICACHE_LINE_SIZE
50 #define __SCB_ICACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). … macro
119 int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U)); in SCB_InvalidateICache_by_Addr()
126 op_addr += __SCB_ICACHE_LINE_SIZE; in SCB_InvalidateICache_by_Addr()
127 op_size -= __SCB_ICACHE_LINE_SIZE; in SCB_InvalidateICache_by_Addr()
/bsp/renesas/ra8d1-ek/ra/arm/CMSIS_5/CMSIS/Core/Include/
A Dcachel1_armv7.h49 #ifndef __SCB_ICACHE_LINE_SIZE
50 #define __SCB_ICACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). … macro
119 int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U)); in SCB_InvalidateICache_by_Addr()
126 op_addr += __SCB_ICACHE_LINE_SIZE; in SCB_InvalidateICache_by_Addr()
127 op_size -= __SCB_ICACHE_LINE_SIZE; in SCB_InvalidateICache_by_Addr()
/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/
A Dcachel1_armv7.h49 #ifndef __SCB_ICACHE_LINE_SIZE
50 #define __SCB_ICACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). … macro
119 int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U)); in SCB_InvalidateICache_by_Addr()
126 op_addr += __SCB_ICACHE_LINE_SIZE; in SCB_InvalidateICache_by_Addr()
127 op_size -= __SCB_ICACHE_LINE_SIZE; in SCB_InvalidateICache_by_Addr()
/bsp/renesas/ra6e2-fpb/ra/arm/CMSIS_6/CMSIS/Core/Include/m-profile/
A Darmv7m_cachel1.h47 #ifndef __SCB_ICACHE_LINE_SIZE
48 #define __SCB_ICACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). … macro
117 int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U)); in SCB_InvalidateICache_by_Addr()
124 op_addr += __SCB_ICACHE_LINE_SIZE; in SCB_InvalidateICache_by_Addr()
125 op_size -= __SCB_ICACHE_LINE_SIZE; in SCB_InvalidateICache_by_Addr()
/bsp/renesas/ra4e2-eco/ra/arm/CMSIS_6/CMSIS/Core/Include/m-profile/
A Darmv7m_cachel1.h47 #ifndef __SCB_ICACHE_LINE_SIZE
48 #define __SCB_ICACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). … macro
118 int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U)); in SCB_InvalidateICache_by_Addr()
125 op_addr += __SCB_ICACHE_LINE_SIZE; in SCB_InvalidateICache_by_Addr()
126 op_size -= __SCB_ICACHE_LINE_SIZE; in SCB_InvalidateICache_by_Addr()
/bsp/at32/libraries/CMSIS/include/
A Dcachel1_armv7.h49 #ifndef __SCB_ICACHE_LINE_SIZE
50 #define __SCB_ICACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). … macro
119 int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U)); in SCB_InvalidateICache_by_Addr()
126 op_addr += __SCB_ICACHE_LINE_SIZE; in SCB_InvalidateICache_by_Addr()
127 op_size -= __SCB_ICACHE_LINE_SIZE; in SCB_InvalidateICache_by_Addr()
/bsp/hc32l196/Libraries/CMSIS/Include/
A Dcore_cm7.h2235 #define __SCB_ICACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). … macro
2303 int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U)); in SCB_InvalidateICache_by_Addr()
2310 op_addr += __SCB_ICACHE_LINE_SIZE; in SCB_InvalidateICache_by_Addr()
2311 op_size -= __SCB_ICACHE_LINE_SIZE; in SCB_InvalidateICache_by_Addr()
/bsp/hc32l136/Libraries/CMSIS/Include/
A Dcore_cm7.h2235 #define __SCB_ICACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). … macro
2303 int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U)); in SCB_InvalidateICache_by_Addr()
2310 op_addr += __SCB_ICACHE_LINE_SIZE; in SCB_InvalidateICache_by_Addr()
2311 op_size -= __SCB_ICACHE_LINE_SIZE; in SCB_InvalidateICache_by_Addr()
/bsp/mm32/libraries/MM32F3270_HAL/CMSIS/Include/
A Dcore_cm7.h2235 #define __SCB_ICACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). … macro
2303 int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U)); in SCB_InvalidateICache_by_Addr()
2310 op_addr += __SCB_ICACHE_LINE_SIZE; in SCB_InvalidateICache_by_Addr()
2311 op_size -= __SCB_ICACHE_LINE_SIZE; in SCB_InvalidateICache_by_Addr()
/bsp/nrf5x/libraries/cmsis/include/
A Dcore_cm7.h2235 #define __SCB_ICACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). … macro
2303 int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U)); in SCB_InvalidateICache_by_Addr()
2310 op_addr += __SCB_ICACHE_LINE_SIZE; in SCB_InvalidateICache_by_Addr()
2311 op_size -= __SCB_ICACHE_LINE_SIZE; in SCB_InvalidateICache_by_Addr()

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