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/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/
A Dhpm_wdg_regs.h15 __W uint32_t RESTART; /* 0x14: Restart Register */
16 __W uint32_t WREN; /* 0x18: Write Protection Register */
17 __W uint32_t ST; /* 0x1C: Status Register */
A Dhpm_dma_regs.h16 __W uint32_t DMACTRL; /* 0x20: DMAC Control Register */
17 __W uint32_t CHABORT; /* 0x24: Channel Abort Register */
19 __W uint32_t INTSTATUS; /* 0x30: Interrupt Status Register */
A Dhpm_mbx_regs.h15 __W uint32_t TXREG; /* 0x8: Transmit word message to other core. */
17 __W uint32_t TXWRD[1]; /* 0x10: TXFIFO for sending message to other core */
A Dhpm_ppor_regs.h13 __W uint32_t RESET_FLAG; /* 0x0: flag indicate reset source */
/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/
A Dhpm_wdg_regs.h15 __W uint32_t RESTART; /* 0x14: Restart Register */
16 __W uint32_t WREN; /* 0x18: Write Protection Register */
17 __W uint32_t ST; /* 0x1C: Status Register */
A Dhpm_dma_regs.h16 __W uint32_t DMACTRL; /* 0x20: DMAC Control Register */
17 __W uint32_t CHABORT; /* 0x24: Channel Abort Register */
19 __W uint32_t INTSTATUS; /* 0x30: Interrupt Status Register */
A Dhpm_mbx_regs.h15 __W uint32_t TXREG; /* 0x8: Transmit word message to other core. */
17 __W uint32_t TXWRD[1]; /* 0x10: TXFIFO for sending message to other core */
A Dhpm_ppor_regs.h13 __W uint32_t RESET_FLAG; /* 0x0: flag indicate reset source */
/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/
A Dhpm_wdg_regs.h15 __W uint32_t RESTART; /* 0x14: Restart Register */
16 __W uint32_t WREN; /* 0x18: Write Protection Register */
17 __W uint32_t ST; /* 0x1C: Status Register */
A Dhpm_dma_regs.h18 __W uint32_t DMACTRL; /* 0x20: DMAC Control Register */
19 __W uint32_t CHABORT; /* 0x24: Channel Abort Register */
21 __W uint32_t INTSTATUS; /* 0x30: Interrupt Status Register */
A Dhpm_mbx_regs.h15 __W uint32_t TXREG; /* 0x8: Transmit word message to other core. */
17 __W uint32_t TXWRD[1]; /* 0x10: TXFIFO for sending message to other core */
A Dhpm_ppor_regs.h13 __W uint32_t RESET_FLAG; /* 0x0: flag indicate reset source */
/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/
A Dhpm_dmav2_regs.h17 __W uint32_t DMACTRL; /* 0x14: DMAC Control Register */
18 __W uint32_t CHABORT; /* 0x18: Channel Abort Register */
21 __W uint32_t INTTCSTS; /* 0x28: Trans Complete Interrupt Status Register */
22 __W uint32_t INTABORTSTS; /* 0x2C: Abort Interrupt Status Register */
23 __W uint32_t INTERRSTS; /* 0x30: Error Interrupt Status Register */
A Dhpm_mbx_regs.h15 __W uint32_t TXREG; /* 0x8: Transmit word message to other core. */
17 __W uint32_t TXWRD[1]; /* 0x10: TXFIFO for sending message to other core */
A Dhpm_ppor_regs.h13 __W uint32_t RESET_FLAG; /* 0x0: flag indicate reset source */
/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/
A Dhpm_dmav2_regs.h17 __W uint32_t DMACTRL; /* 0x14: DMAC Control Register */
18 __W uint32_t CHABORT; /* 0x18: Channel Abort Register */
21 __W uint32_t INTTCSTS; /* 0x28: Trans Complete Interrupt Status Register */
22 __W uint32_t INTABORTSTS; /* 0x2C: Abort Interrupt Status Register */
23 __W uint32_t INTERRSTS; /* 0x30: Error Interrupt Status Register */
A Dhpm_mbx_regs.h15 __W uint32_t TXREG; /* 0x8: Transmit word message to other core. */
17 __W uint32_t TXWRD[1]; /* 0x10: TXFIFO for sending message to other core */
A Dhpm_dmamux_regs.h13 __W uint32_t MUXCFG[64]; /* 0x0 - 0xFC: HDMA MUX0 Configuration */
A Dhpm_ppor_regs.h13 __W uint32_t RESET_FLAG; /* 0x0: flag indicate reset source */
A Dhpm_pwmv2_regs.h45 __W uint32_t IRQ_STS_CMP; /* 0x410: */
46 __W uint32_t IRQ_STS_RELOAD; /* 0x414: */
47 __W uint32_t IRQ_STS_CAP_POS; /* 0x418: */
48 __W uint32_t IRQ_STS_CAP_NEG; /* 0x41C: */
49 __W uint32_t IRQ_STS_FAULT; /* 0x420: */
50 __W uint32_t IRQ_STS_BURSTEND; /* 0x424: */
/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/ip/
A Dhpm_dmav2_regs.h17 __W uint32_t DMACTRL; /* 0x14: DMAC Control Register */
18 __W uint32_t CHABORT; /* 0x18: Channel Abort Register */
21 __W uint32_t INTTCSTS; /* 0x28: Trans Complete Interrupt Status Register */
22 __W uint32_t INTABORTSTS; /* 0x2C: Abort Interrupt Status Register */
23 __W uint32_t INTERRSTS; /* 0x30: Error Interrupt Status Register */
A Dhpm_dmamux_regs.h13 __W uint32_t MUXCFG[32]; /* 0x0 - 0x7C: HDMA MUX0 Configuration */
A Dhpm_mbx_regs.h15 __W uint32_t TXREG; /* 0x8: Transmit word message to other core. */
17 __W uint32_t TXWRD[1]; /* 0x10: TXFIFO for sending message to other core */
A Dhpm_ppor_regs.h13 __W uint32_t RESET_FLAG; /* 0x0: flag indicate reset source */
/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/
A Dhpm_common.h27 #define __W volatile /* Define "write-only" permission */ macro
38 #define __O __W

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