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/bsp/allwinner/libraries/sunxi-hal/hal/source/ccmu/sunxi-ng/
A Dccu_gate.h20 #define SUNXI_CCU_GATE_WITH_FIXED_RATE(_struct, _name, _parent, _reg, \ argument
35 #define SUNXI_CCU_GATE_WITH_PREDIV(_struct, _name, _parent, _reg, \ argument
43 .hw.init = CLK_HW_INIT(_name, \
50 #define SUNXI_CCU_GATE_WITH_KEY(_struct, _name, _parent, _reg, \ argument
58 .hw.init = CLK_HW_INIT(_name, \
65 #define SUNXI_CCU_GATE(_struct, _name, _parent, _reg, _gate, _flags) \ argument
70 .hw.init = CLK_HW_INIT(_name, \
77 #define SUNXI_CCU_GATE_HW(_struct, _name, _parent, _reg, _gate, _flags) \ argument
89 #define SUNXI_CCU_GATE_FW(_struct, _name, _parent, _reg, _gate, _flags) \ argument
105 #define SUNXI_CCU_GATE_HWS(_struct, _name, _parent, _reg, _gate, _flags) \ argument
[all …]
A Dccu_div.h88 #define SUNXI_CCU_DIV_TABLE_WITH_GATE(_struct, _name, _parent, _reg, \ argument
105 #define SUNXI_CCU_DIV_TABLE(_struct, _name, _parent, _reg, \ argument
108 SUNXI_CCU_DIV_TABLE_WITH_GATE(_struct, _name, _parent, _reg, \
112 #define SUNXI_CCU_M_WITH_MUX_TABLE_GATE(_struct, _name, \ argument
131 #define SUNXI_CCU_M_WITH_MUX_GATE(_struct, _name, _parents, _reg, \ argument
134 SUNXI_CCU_M_WITH_MUX_TABLE_GATE(_struct, _name, \
140 #define SUNXI_CCU_M_WITH_MUX(_struct, _name, _parents, _reg, \ argument
143 SUNXI_CCU_M_WITH_MUX_TABLE_GATE(_struct, _name, \
150 #define SUNXI_CCU_M_WITH_GATE(_struct, _name, _parent, _reg, \ argument
165 #define SUNXI_CCU_M(_struct, _name, _parent, _reg, _mshift, _mwidth, \ argument
[all …]
A Dccu_mp.h33 #define SUNXI_CCU_MP_WITH_MUX_GATE_NO_INDEX(_struct, _name, _parents, _reg, \ argument
46 … .hw.init = CLK_HW_INIT_PARENTS(_name, \
53 #define SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(_struct, _name, _parents, _reg, \ argument
67 … .hw.init = CLK_HW_INIT_PARENTS(_name, \
74 #define SUNXI_CCU_MP_WITH_MUX_GATE(_struct, _name, _parents, _reg, \ argument
86 … .hw.init = CLK_HW_INIT_PARENTS(_name, \
93 #define SUNXI_CCU_MP_WITH_MUX(_struct, _name, _parents, _reg, \ argument
98 SUNXI_CCU_MP_WITH_MUX_GATE(_struct, _name, _parents, _reg, \
122 #define SUNXI_CCU_MP_MMC_WITH_MUX_GATE(_struct, _name, _parents, _reg, \ argument
132 … .hw.init = CLK_HW_INIT_PARENTS(_name, \
A Dccu.h625 #define CLK_HW_INIT(_name, _parent, _ops, _flags) \ argument
628 .name = _name, \
637 .name = _name, \
651 .name = _name, \
660 .name = _name, \
668 #define CLK_HW_INIT_PARENTS(_name, _parents, _ops, _flags) \ argument
671 .name = _name, \
680 .name = _name, \
689 .name = _name, \
695 #define CLK_HW_INIT_NO_PARENT(_name, _ops, _flags) \ argument
[all …]
A Dccu_nm.h38 #define SUNXI_CCU_NM_WITH_SDM_GATE_LOCK(_struct, _name, _parent, _reg, \ argument
54 … .hw.init = CLK_HW_INIT(_name, \
61 #define SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(_struct, _name, _parent, _reg, \ argument
78 … .hw.init = CLK_HW_INIT(_name, \
85 #define SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN(_struct, _name, _parent, \ argument
104 … .hw.init = CLK_HW_INIT(_name, \
111 #define SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX(_struct, _name, \ argument
133 … .hw.init = CLK_HW_INIT(_name, \
140 #define SUNXI_CCU_NM_WITH_GATE_LOCK(_struct, _name, _parent, _reg, \ argument
151 … .hw.init = CLK_HW_INIT(_name, \
A Dccu_mux.h59 #define SUNXI_CCU_MUX_WITH_GATE_KEY(_struct, _name, _parents, \ argument
69 … .hw.init = CLK_HW_INIT_PARENTS(_name, \
76 #define SUNXI_CCU_MUX_TABLE_WITH_GATE(_struct, _name, _parents, _table, \ argument
84 … .hw.init = CLK_HW_INIT_PARENTS(_name, \
91 #define SUNXI_CCU_MUX_WITH_GATE(_struct, _name, _parents, _reg, \ argument
93 SUNXI_CCU_MUX_TABLE_WITH_GATE(_struct, _name, _parents, NULL, \
97 #define SUNXI_CCU_MUX(_struct, _name, _parents, _reg, _shift, _width, \ argument
99 SUNXI_CCU_MUX_TABLE_WITH_GATE(_struct, _name, _parents, NULL, \
A Dccu_nkm.h34 #define SUNXI_CCU_NKM_WITH_MUX_GATE_LOCK(_struct, _name, _parents, _reg, \ argument
49 … .hw.init = CLK_HW_INIT_PARENTS(_name, \
56 #define SUNXI_CCU_NKM_WITH_GATE_LOCK(_struct, _name, _parent, _reg, \ argument
69 … .hw.init = CLK_HW_INIT(_name, \
A Dccu_phase.h20 #define SUNXI_CCU_PHASE(_struct, _name, _parent, _reg, _shift, _width, _flags) \ argument
26 … .hw.init = CLK_HW_INIT(_name, \
A Dccu_nk.h33 #define SUNXI_CCU_NK_WITH_GATE_LOCK_POSTDIV(_struct, _name, _parent, _reg, \ argument
47 … .hw.init = CLK_HW_INIT(_name, \
A Dccu_nkmp.h35 #define SUNXI_CCU_NKMP_WITH_GATE_LOCK(_struct, _name, _parent, _reg, \ argument
50 … .hw.init = CLK_HW_INIT(_name, \
A Dccu_mult.h47 #define SUNXI_CCU_N_WITH_GATE_LOCK(_struct, _name, _parent, _reg, \ argument
56 … .hw.init = CLK_HW_INIT(_name, \
/bsp/allwinner/libraries/sunxi-hal/hal/source/ccmu/sunxi/
A Dclk_factors.h96 #define SUNXI_CLK_FACTORS_INIT(_name, _reg, _lock_reg, _lock_bit, _pll_lock_ctrl_reg, _lock_en_bit … argument
97 struct factor_init_data sunxi_clk_factor_init_##_name = { \
104 … .config = &sunxi_clk_factor_config_##_name, \
105 … .get_factors = &get_factors_##_name, \
106 … .calc_rate = &calc_rate_##_name, \
109 #define SUNXI_CLK_FACTOR(_name, _clk, _current_parent, _current_parent_type, _clk_rate, _parent_ra… argument
110 clk_factor_t sunxi_clk_factor_##_name = { \
120 .factor_data = &sunxi_clk_factor_init_##_name, \
A Dclk_periph.h71 #define SUNXI_CLK_PERIPH(_name, _clk, _parent_arry) \ argument
72 clk_periph_t sunxi_clk_periph_##_name = { \
84 .config = &sunxi_clk_periph_config_##_name, \
87 #define SUNXI_PERIPH_INIT(_name, _clk, _parent_clk, _clk_rate) \ argument
88 clk_base_t sunxi_periph_clk_init_##_name = { \
A Dclk.h105 #define SUNXI_CLK_FIXED_SRC(_name, _clk, _current_parent, _current_parent_type, _clk_rate, _parent_… argument
106 clk_core_t sunxi_clk_fixed_src_##_name = { \
120 #define SUNXI_CLK_FIXED_FACTOR(_name, _clk, _current_parent, _current_parent_type, _mult, _div) \ argument
121 clk_fixed_factor_t sunxi_clk_fixed_factor_##_name = { \
/bsp/rockchip/rk3500/driver/clk/
A Dclk-rk3568.h69 #define GATE(_id, _name, \ argument
73 .name = _name, \
A Dclk-rk3588.h94 #define GATE(_id, _name, \ argument
98 .name = _name, \
A Dclk-rk3588.c518 #define GATE(_id, _name, \ argument
522 .name = _name, \
/bsp/allwinner/libraries/sunxi-hal/hal/source/sdmmc/
A D_core.h200 #define _FIXUP_EXT(_name, _manfid, _oemid, _rev_start, _rev_end, \ argument
204 .name = (_name), \
/bsp/allwinner/libraries/sunxi-hal/hal/test/ccmu/
A Dtest_ccmu.c222 #define ccmuapi_test(_func, _id, _name, _result) \ argument

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