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/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/
A Dhpm_common.h209 #define ATTR_ALIGN(alignment) __attribute__((aligned(alignment))) argument
216 ATTR_PLACE_AT(section_name) ATTR_ALIGN(alignment)
220 ATTR_PLACE_AT_NONCACHEABLE ATTR_ALIGN(alignment)
224 ATTR_PLACE_AT_NONCACHEABLE_BSS ATTR_ALIGN(alignment)
229 ATTR_PLACE_AT_NONCACHEABLE_INIT ATTR_ALIGN(alignment)
233 #define ATTR_PLACE_AT_FAST_RAM_WITH_ALIGNMENT(alignment) \ argument
234 ATTR_PLACE_AT_FAST_RAM ATTR_ALIGN(alignment)
238 ATTR_PLACE_AT_FAST_RAM_BSS ATTR_ALIGN(alignment)
242 ATTR_PLACE_AT_FAST_RAM_INIT ATTR_ALIGN(alignment)
245 #define ATTR_RAMFUNC_WITH_ALIGNMENT(alignment) \ argument
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/bsp/beaglebone/
A Dam335x_DDR.icf25 define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
26 define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { };
27 define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { };
28 define block FIQ_STACK with alignment = 8, size = __ICFEDIT_size_fiqstack__ { };
29 define block UND_STACK with alignment = 8, size = __ICFEDIT_size_undstack__ { };
30 define block ABT_STACK with alignment = 8, size = __ICFEDIT_size_abtstack__ { };
31 define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
A Dbeaglebone_ram.icf25 define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
26 define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { };
27 define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { };
28 define block FIQ_STACK with alignment = 8, size = __ICFEDIT_size_fiqstack__ { };
29 define block UND_STACK with alignment = 8, size = __ICFEDIT_size_undstack__ { };
30 define block ABT_STACK with alignment = 8, size = __ICFEDIT_size_abtstack__ { };
31 define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
/bsp/renesas/rzn2l_rsk/script/
A Dfsp_xspi0_boot.icf535 define block LDR_DATA_ZBLOCK with alignment = 4
547 define block LDR_DATA_RBLOCK with fixed order, alignment = 4
559 define block LDR_DATA_WBLOCK with fixed order, alignment = 4
572 define block HEAP_BLOCK with alignment = 8 { rw section HEAP };
573 define block THREAD_STACK with alignment = 8 { rw section .stack* };
574 define block SYS_STACK with alignment = 8 { rw section .sys_stack };
583 define block USER_PRG_RBLOCK with alignment = 4 { ro code };
584 define block USER_PRG_WBLOCK with alignment = 4 { rw code };
585 define block USER_DATA_ZBLOCK with alignment = 4 { section .bss };
586 define block USER_DATA_RBLOCK with fixed order, alignment = 4
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/bsp/renesas/rzt2m_rsk/script/
A Dfsp_xspi0_boot.icf565 define block LDR_DATA_ZBLOCK with alignment = 4
578 define block LDR_DATA_RBLOCK with fixed order, alignment = 4
591 define block LDR_DATA_WBLOCK with fixed order, alignment = 4
605 define block HEAP_BLOCK with alignment = 8 { rw section HEAP };
606 define block THREAD_STACK with alignment = 8 { rw section .stack* };
607 define block SYS_STACK with alignment = 8 { rw section .sys_stack };
616 define block USER_PRG_RBLOCK with alignment = 4 { ro code };
617 define block USER_PRG_WBLOCK with alignment = 4 { rw code };
618 define block USER_DATA_ZBLOCK with alignment = 4 { section .bss };
619 define block USER_DATA_RBLOCK with fixed order, alignment = 4
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/bsp/renesas/rzn2l_etherkit/script/
A Dfsp_xspi0_boot.icf586 define block LDR_DATA_ZBLOCK with alignment = 4
598 define block LDR_DATA_RBLOCK with fixed order, alignment = 4
610 define block LDR_DATA_WBLOCK with fixed order, alignment = 4
623 define block HEAP_BLOCK with alignment = 8 { rw section HEAP };
624 define block THREAD_STACK with alignment = 8 { rw section .stack* };
625 define block SYS_STACK with alignment = 8 { rw section .sys_stack };
634 define block USER_PRG_RBLOCK with alignment = 4 { ro code };
635 define block USER_PRG_WBLOCK with alignment = 4 { rw code };
636 define block USER_DATA_ZBLOCK with alignment = 4 { section .bss };
637 define block USER_DATA_RBLOCK with fixed order, alignment = 4
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/bsp/mm32l3xx/drivers/linker_scripts/
A Dlink.icf19 define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
20 define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { };
21 define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
/bsp/mm32f327x/drivers/linker_scripts/
A Dlink.icf19 define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
20 define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { };
21 define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
/bsp/mm32f526x/board/linker_scripts/
A Dlink.icf19 define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
20 define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { };
21 define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
/bsp/mm32f526x/drivers/linker_scripts/
A Dlink.icf19 define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
20 define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { };
21 define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
/bsp/tkm32F499/drivers/linker_scripts/
A Dlink.icf19 define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
20 define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { };
21 define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
/bsp/mm32l07x/drivers/linker_scripts/
A Dlink.icf19 define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
20 define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { };
21 define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
/bsp/mm32f103x/drivers/linker_scripts/
A Dlink.icf19 define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
20 define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { };
21 define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
/bsp/renesas/ra8d1-ek/script/
A Dfsp.scat258 ; This avoids memory holes due to 1K alignment required by it.
291 ; The required minimum ending alignment is a 32 byte boundary for Armv8-M MPU requirements.
292 …; There is no way to control the ending alignment of NOCACHE, so this dedicated section acts as pa…
416 ; The required minimum execution address alignment is an 8 byte boundary for ECC compatibility.
427 ; The required minimum ending alignment is an 8 byte boundary for ECC compatibility.
428 …; There is no way to control the ending alignment of ITCM_DATA, so this dedicated section acts as …
453 ; The required minimum execution address alignment is an 8 byte boundary for ECC compatibility.
464 ; The required minimum ending alignment is an 8 byte boundary for ECC compatibility.
479 ; The required minimum ending alignment is an 8 byte boundary for ECC compatibility.
480 …; There is no way to control the ending alignment of DTCM_BSS, so this dedicated section acts as p…
[all …]
/bsp/renesas/ra8m1-ek/script/
A Dfsp.scat258 ; This avoids memory holes due to 1K alignment required by it.
291 ; The required minimum ending alignment is a 32 byte boundary for Armv8-M MPU requirements.
292 …; There is no way to control the ending alignment of NOCACHE, so this dedicated section acts as pa…
416 ; The required minimum execution address alignment is an 8 byte boundary for ECC compatibility.
427 ; The required minimum ending alignment is an 8 byte boundary for ECC compatibility.
428 …; There is no way to control the ending alignment of ITCM_DATA, so this dedicated section acts as …
453 ; The required minimum execution address alignment is an 8 byte boundary for ECC compatibility.
464 ; The required minimum ending alignment is an 8 byte boundary for ECC compatibility.
479 ; The required minimum ending alignment is an 8 byte boundary for ECC compatibility.
480 …; There is no way to control the ending alignment of DTCM_BSS, so this dedicated section acts as p…
[all …]
/bsp/renesas/ra8d1-vision-board/script/
A Dfsp.scat258 ; This avoids memory holes due to 1K alignment required by it.
291 ; The required minimum ending alignment is a 32 byte boundary for Armv8-M MPU requirements.
292 …; There is no way to control the ending alignment of NOCACHE, so this dedicated section acts as pa…
416 ; The required minimum execution address alignment is an 8 byte boundary for ECC compatibility.
427 ; The required minimum ending alignment is an 8 byte boundary for ECC compatibility.
428 …; There is no way to control the ending alignment of ITCM_DATA, so this dedicated section acts as …
453 ; The required minimum execution address alignment is an 8 byte boundary for ECC compatibility.
464 ; The required minimum ending alignment is an 8 byte boundary for ECC compatibility.
479 ; The required minimum ending alignment is an 8 byte boundary for ECC compatibility.
480 …; There is no way to control the ending alignment of DTCM_BSS, so this dedicated section acts as p…
[all …]
/bsp/rx/
A Dlnkr5f562n8.icf18 define block HEAP with alignment = 4, size = _HEAP_SIZE { };
19 define block USTACK with alignment = 4, size = _USTACK_SIZE { };
20 define block ISTACK with alignment = 4, size = _ISTACK_SIZE { };
/bsp/msp432e401y-LaunchPad/board/linker_scripts/
A Dlink.icf45 define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { };
46 define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
47 define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
/bsp/nxp/imx/imxrt/libraries/drivers/vglite/VGLiteKernel/
A Dvg_lite_kernel.h46 #define VG_LITE_ALIGN(number, alignment) \ argument
47 (((number) + ((alignment) - 1)) & ~((alignment) - 1))
/bsp/synwit/swm320-mini/board/linker_scripts/
A Dlink.icf45 define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
46 define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { };
47 define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
/bsp/synwit/swm341-mini/board/linker_scripts/
A Dlink.icf45 define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
46 define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { };
47 define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
/bsp/renesas/ra6m3-hmi-board/script/
A Dfsp.scat251 ; This avoids memory holes due to 1K alignment required by it.
398 ; The required minimum execution address alignment is an 8 byte boundary for ECC compatibility.
409 ; The required minimum ending alignment is an 8 byte boundary for ECC compatibility.
410 …; There is no way to control the ending alignment of ITCM_DATA, so this dedicated section acts as …
435 ; The required minimum execution address alignment is an 8 byte boundary for ECC compatibility.
446 ; The required minimum ending alignment is an 8 byte boundary for ECC compatibility.
447 …; There is no way to control the ending alignment of DTCM_DATA, so this dedicated section acts as …
461 ; The required minimum ending alignment is an 8 byte boundary for ECC compatibility.
462 …; There is no way to control the ending alignment of DTCM_BSS, so this dedicated section acts as p…
/bsp/renesas/ra4e2-eco/script/
A Dfsp.scat266 ; This avoids memory holes due to 1K alignment required by it.
413 ; The required minimum execution address alignment is an 8 byte boundary for ECC compatibility.
424 ; The required minimum ending alignment is an 8 byte boundary for ECC compatibility.
425 …; There is no way to control the ending alignment of ITCM_DATA, so this dedicated section acts as …
450 ; The required minimum execution address alignment is an 8 byte boundary for ECC compatibility.
461 ; The required minimum ending alignment is an 8 byte boundary for ECC compatibility.
462 …; There is no way to control the ending alignment of DTCM_DATA, so this dedicated section acts as …
476 ; The required minimum ending alignment is an 8 byte boundary for ECC compatibility.
477 …; There is no way to control the ending alignment of DTCM_BSS, so this dedicated section acts as p…
/bsp/renesas/ra6e2-fpb/script/
A Dfsp.scat255 ; This avoids memory holes due to 1K alignment required by it.
402 ; The required minimum execution address alignment is an 8 byte boundary for ECC compatibility.
413 ; The required minimum ending alignment is an 8 byte boundary for ECC compatibility.
414 …; There is no way to control the ending alignment of ITCM_DATA, so this dedicated section acts as …
439 ; The required minimum execution address alignment is an 8 byte boundary for ECC compatibility.
450 ; The required minimum ending alignment is an 8 byte boundary for ECC compatibility.
451 …; There is no way to control the ending alignment of DTCM_DATA, so this dedicated section acts as …
465 ; The required minimum ending alignment is an 8 byte boundary for ECC compatibility.
466 …; There is no way to control the ending alignment of DTCM_BSS, so this dedicated section acts as p…
/bsp/fujitsu/mb9x/mb9bf506r/
A Drtthread-mb9bf506.icf21 define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
22 define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };

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