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Searched refs:base (Results 1 – 25 of 621) sorted by relevance

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/bsp/allwinner/libraries/sunxi-hal/hal/source/disp2/disp/de/lowlevel_v2x/
A Drtmx_eink.c111 unsigned int base;
297 de_writel(base + 0x02018, addr0);
298 de_writel(base + 0x0201c, addr1);
299 de_writel(base + 0x02020, addr2);
471 de_writel(base + 0x20088, yhstep);
472 de_writel(base + 0x2008c, yvstep);
686 unsigned int base; in rt_mixer_init() local
871 de_writel(base + 0x02018, addr0); in rt_mixer_init()
872 de_writel(base + 0x0201c, addr1); in rt_mixer_init()
873 de_writel(base + 0x02020, addr2); in rt_mixer_init()
[all …]
/bsp/beaglebone/drivers/
A Duart_reg.h13 #define UART_DLL(base) (base + 0x0) argument
14 #define UART_RHR(base) (base + 0x0) argument
15 #define UART_THR(base) (base + 0x0) argument
16 #define UART_DLH(base) (base + 0x4) argument
17 #define UART_IER(base) (base + 0x4) argument
18 #define UART_EFR(base) (base + 0x8) argument
19 #define UART_FCR(base) (base + 0x8) argument
20 #define UART_IIR(base) (base + 0x8) argument
21 #define UART_LCR(base) (base + 0xC) argument
22 #define UART_MCR(base) (base + 0x10) argument
[all …]
/bsp/rv32m1_vega/rv32m1_sdk_riscv/devices/RV32M1/drivers/
A Dfsl_trng.c124 #define TRNG_SCML_REG(base) ((base)->SCML) argument
125 #define TRNG_RD_SCML(base) (TRNG_SCML_REG(base)) argument
184 #define TRNG_SCR1L_REG(base) ((base)->SCR1L) argument
247 #define TRNG_SCR2L_REG(base) ((base)->SCR2L) argument
314 #define TRNG_SCR3L_REG(base) ((base)->SCR3L) argument
381 #define TRNG_SCR4L_REG(base) ((base)->SCR4L) argument
448 #define TRNG_SCR5L_REG(base) ((base)->SCR5L) argument
515 #define TRNG_SCR6PL_REG(base) ((base)->SCR6PL) argument
775 #define TRNG_MCTL_REG(base) ((base)->MCTL) argument
956 #define TRNG_SDCTL_REG(base) ((base)->SDCTL) argument
[all …]
A Dfsl_cau3.c879 base->CR = 0U; in cau3_initialize_inst_memory()
2173 base->MDPK = mode; in cau3_pkha_clear_regabne()
3350 base->PKNSZ = size; in CAU3_PKHA_ECC_PointAdd()
3353 base->PKASZ = size; in CAU3_PKHA_ECC_PointAdd()
3358 base->PKBSZ = size; in CAU3_PKHA_ECC_PointAdd()
3422 base->PKNSZ = size; in CAU3_PKHA_ECC_PointDouble()
3425 base->PKASZ = size; in CAU3_PKHA_ECC_PointDouble()
3428 base->PKBSZ = size; in CAU3_PKHA_ECC_PointDouble()
3493 base->PKNSZ = size; in CAU3_PKHA_ECC_PointMul()
3499 base->PKASZ = size; in CAU3_PKHA_ECC_PointMul()
[all …]
A Dfsl_flexio_i2c_master.c154 FLEXIO_ClearShifterErrorFlags(base->flexioBase, 1U << base->shifterIndex[1]); in FLEXIO_I2C_MasterTransferRunStateMachine()
381 FLEXIO_SetShifterConfig(base->flexioBase, base->shifterIndex[0], &shifterConfig); in FLEXIO_I2C_MasterInit()
423 FLEXIO_SetTimerConfig(base->flexioBase, base->timerIndex[0], &timerConfig); in FLEXIO_I2C_MasterInit()
444 FLEXIO_SetTimerConfig(base->flexioBase, base->timerIndex[1], &timerConfig); in FLEXIO_I2C_MasterInit()
484 …((FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1U << base->shifterIndex[0])) >> base->shifter… in FLEXIO_I2C_MasterGetStatusFlags()
486 …(((FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1U << base->shifterIndex[1])) >> (base->shift… in FLEXIO_I2C_MasterGetStatusFlags()
489 …(((FLEXIO_GetShifterErrorFlags(base->flexioBase) & (1U << base->shifterIndex[1])) >> (base->shifte… in FLEXIO_I2C_MasterGetStatusFlags()
604 tmpConfig = base->flexioBase->TIMCFG[base->timerIndex[0]]; in FLEXIO_I2C_MasterAbortStop()
607 base->flexioBase->TIMCFG[base->timerIndex[0]] = tmpConfig; in FLEXIO_I2C_MasterAbortStop()
614 tmpConfig = base->flexioBase->SHIFTCFG[base->shifterIndex[0]]; in FLEXIO_I2C_MasterEnableAck()
[all …]
A Dfsl_tpm.c72 TPM_Reset(base); in TPM_Init()
194 base->MOD = mod; in TPM_SetupPwm()
357 mod = base->MOD; in TPM_UpdatePwmDutycycle()
560 reg = base->FILTER; in TPM_SetupDualEdgeCapture()
563 base->FILTER = reg; in TPM_SetupDualEdgeCapture()
621 reg = base->FILTER; in TPM_SetupQuadDecode()
624 base->FILTER = reg; in TPM_SetupQuadDecode()
645 reg = base->FILTER; in TPM_SetupQuadDecode()
648 base->FILTER = reg; in TPM_SetupQuadDecode()
662 reg = base->QDCTRL; in TPM_SetupQuadDecode()
[all …]
A Dfsl_lpi2c.h483 base->MCR = 0; in LPI2C_MasterReset()
494 base->MCR = (base->MCR & ~LPI2C_MCR_MEN_MASK) | LPI2C_MCR_MEN(enable); in LPI2C_MasterEnable()
516 return base->MSR; in LPI2C_MasterGetStatusFlags()
541 base->MSR = statusMask; in LPI2C_MasterClearStatusFlags()
561 base->MIER |= interruptMask; in LPI2C_MasterEnableInterrupts()
588 return base->MIER; in LPI2C_MasterGetEnabledInterrupts()
940 base->SCR = 0; in LPI2C_SlaveReset()
951 base->SCR = (base->SCR & ~LPI2C_SCR_SEN_MASK) | LPI2C_SCR_SEN(enable); in LPI2C_SlaveEnable()
973 return base->SSR; in LPI2C_SlaveGetStatusFlags()
995 base->SSR = statusMask; in LPI2C_SlaveClearStatusFlags()
[all …]
A Dfsl_spm.h373 *((uint32_t *)versionId) = base->VERID; in SPM_GetVersionId()
399 base->RCTRL |= SPM_RCTRL_REGSEL(ldoMask); in SPM_EnableRegulatorInRunMdoe()
438 base->CORERCNFG = configMask; in SPM_SetCoreLdoRunModeConfig()
449 base->CORELPCNFG = configMask; in SPM_SetCoreLdoLowPowerModeConfig()
493 base->CORESC |= SPM_CORESC_ACKISO_MASK; in SPM_ClearPeriphIOIsolationFlag()
676 base->RFLDOSC = (base->RFLDOSC & ~SPM_RFLDOSC_VDD1P8SEL_MASK) | SPM_RFLDOSC_VDD1P8SEL(pin); in SPM_SelectVdd1p8SnsPin()
704 …base->DCDCSC = (base->DCDCSC & ~SPM_DCDCSC_DCDC_VBAT_DIV_CTRL_MASK) | SPM_DCDCSC_DCDC_VBAT_DIV_CTR… in SPM_SetDcdcVbatAdcMeasure()
761 base->DCDCC3 = (base->DCDCC3 & ~0xE000000U) | ((uint32_t)(strength) << 25); in SPM_SetDcdcDriveStrength()
808 …base->DCDCC6 = (base->DCDCC6 & ~SPM_DCDCC6_DCDC_HSVDD_TRIM_MASK) | SPM_DCDCC6_DCDC_HSVDD_TRIM(valu… in SPM_SetDcdcVdd1p2ValueHsrun()
821 base->DCDCC6 = in SPM_SetDcdcVdd1p2ValueBuck()
[all …]
/bsp/asm9260t/IAR_ASM9260T_DeviceSupportFile/arm/config/debugger/AlphaScale/
A DioASM9260T.ddf24 sfr = "PRESETCTRL0", "Memory", 0x80040000, 4, base=16
25 sfr = "PRESETCTRL1", "Memory", 0x80040010, 4, base=16
26 sfr = "AHBCLKCTRL0", "Memory", 0x80040020, 4, base=16
29 sfr = "AHBCLKCTRL1", "Memory", 0x80040030, 4, base=16
32 sfr = "SYSPLLCTRL", "Memory", 0x80040100, 4, base=16
33 sfr = "SYSRSTSTAT", "Memory", 0x80040110, 4, base=16
34 sfr = "MAINCLKSEL", "Memory", 0x80040120, 4, base=16
35 sfr = "MAINCLKUEN", "Memory", 0x80040124, 4, base=16
36 sfr = "UARTCLKSEL", "Memory", 0x80040128, 4, base=16
37 sfr = "UARTCLKUEN", "Memory", 0x8004012C, 4, base=16
[all …]
/bsp/frdm-k64f/device/MK64F12/
A Dfsl_flexcan.c467 FLEXCAN_Reset(base); in FLEXCAN_Init()
470 mcrTemp = base->MCR; in FLEXCAN_Init()
476 …base->CTRL1 = (config->enableLoopBack) ? base->CTRL1 | CAN_CTRL1_LPB_MASK : base->CTRL1 & ~CAN_CTR… in FLEXCAN_Init()
490 base->MCR = mcrTemp; in FLEXCAN_Init()
502 FLEXCAN_Reset(base); in FLEXCAN_Deinit()
550 base->CTRL1 |= in FLEXCAN_SetTimingConfig()
724 base->MCR = (base->MCR & ~CAN_MCR_IDAM_MASK) | CAN_MCR_IDAM(0x0); in FLEXCAN_SetRxFifoConfig()
727 base->MCR = (base->MCR & ~CAN_MCR_IDAM_MASK) | CAN_MCR_IDAM(0x1); in FLEXCAN_SetRxFifoConfig()
730 base->MCR = (base->MCR & ~CAN_MCR_IDAM_MASK) | CAN_MCR_IDAM(0x2); in FLEXCAN_SetRxFifoConfig()
734 base->MCR = (base->MCR & ~CAN_MCR_IDAM_MASK) | CAN_MCR_IDAM(0x3); in FLEXCAN_SetRxFifoConfig()
[all …]
A Dfsl_rnga.c53 #define RNG_CR_REG(base) ((base)->CR) argument
54 #define RNG_RD_CR(base) (RNG_CR_REG(base)) argument
55 #define RNG_WR_CR(base, value) (RNG_CR_REG(base) = (value)) argument
56 #define RNG_RMW_CR(base, mask, value) (RNG_WR_CR(base, (RNG_RD_CR(base) & ~(mask)) | (value))) argument
99 #define RNG_SR_REG(base) ((base)->SR) argument
147 #define RNG_OR_REG(base) ((base)->OR) argument
148 #define RNG_RD_OR(base) (RNG_OR_REG(base)) argument
167 #define RNG_ER_REG(base) ((base)->ER) argument
168 #define RNG_RD_ER(base) (RNG_ER_REG(base)) argument
169 #define RNG_WR_ER(base, value) (RNG_ER_REG(base) = (value)) argument
[all …]
A Dfsl_i2c.c487 base->A1 = 0; in I2C_MasterInit()
488 base->F = 0; in I2C_MasterInit()
489 base->C1 = 0; in I2C_MasterInit()
491 base->C2 = 0; in I2C_MasterInit()
497 base->RA = 0; in I2C_MasterInit()
957 result = I2C_CheckAndClearError(base, base->S); in I2C_MasterTransferBlocking()
989 result = I2C_CheckAndClearError(base, base->S); in I2C_MasterTransferBlocking()
1023 result = I2C_CheckAndClearError(base, base->S); in I2C_MasterTransferBlocking()
1214 base->A1 = 0; in I2C_SlaveInit()
1215 base->F = 0; in I2C_SlaveInit()
[all …]
A Dfsl_ftm.c111 reg = base->COMBINE; in FTM_SetPwmSync()
117 base->COMBINE = reg; in FTM_SetPwmSync()
119 reg = base->SYNCONF; in FTM_SetPwmSync()
156 base->SYNCONF = reg; in FTM_SetPwmSync()
167 reg = base->COMBINE; in FTM_SetReloadPoints()
173 base->COMBINE = reg; in FTM_SetReloadPoints()
176 reg = base->PWMLOAD; in FTM_SetReloadPoints()
197 reg = base->SYNC; in FTM_SetReloadPoints()
217 base->SYNC = reg; in FTM_SetReloadPoints()
370 base->MOD = mod; in FTM_SetupPwm()
[all …]
A Dfsl_sai.c488 base->TCR2 = 0; in SAI_TxReset()
489 base->TCR3 = 0; in SAI_TxReset()
490 base->TCR4 = 0; in SAI_TxReset()
491 base->TCR5 = 0; in SAI_TxReset()
492 base->TMR = 0; in SAI_TxReset()
504 base->RCR2 = 0; in SAI_RxReset()
505 base->RCR3 = 0; in SAI_RxReset()
506 base->RCR4 = 0; in SAI_RxReset()
507 base->RCR5 = 0; in SAI_RxReset()
508 base->RMR = 0; in SAI_RxReset()
[all …]
/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/
A Dhpm_can_drv.h314 base->CMD_STA_CMD_CTRL = cfg_stat; in can_set_node_mode()
641 base->RTIE |= mask; in can_enable_tx_rx_irq()
651 base->RTIE &= ~mask; in can_disable_tx_rx_irq()
661 base->RTIF = flags; in can_clear_tx_rx_flags()
672 return base->RTIF; in can_get_tx_rx_flags()
682 base->ERRINT |= mask; in can_enable_error_irq()
693 base->ERRINT &= ~mask; in can_disable_error_irq()
714 base->ERRINT |= flags; in can_clear_error_interrupt_flags()
773 return base->RECNT; in can_get_receive_error_count()
783 return base->TECNT; in can_get_transmit_error_count()
[all …]
A Dhpm_qeov2_drv.h165 …base->WAVE.MODE = (base->WAVE.MODE & ~QEOV2_WAVE_MODE_WAVES_OUTPUT_TYPE_MASK) | QEOV2_WAVE_MODE_WA… in qeo_wave_set_output_type()
203 base->WAVE.MODE |= QEOV2_WAVE_MODE_VD_VQ_SEL_MASK; in qeo_wave_enable_vd_vq_inject()
205 base->WAVE.MODE &= ~QEOV2_WAVE_MODE_VD_VQ_SEL_MASK; in qeo_wave_enable_vd_vq_inject()
235 static inline void qeo_wave_load_vd_vq(QEOV2_Type *base) in qeo_wave_load_vd_vq() argument
334 return QEOV2_DEBUG0_VALUE_DAC0_GET(base->DEBUG0); in qeo_get_wave_output_val()
336 return QEOV2_DEBUG4_VALUE_DAC1_GET(base->DEBUG4); in qeo_get_wave_output_val()
338 return QEOV2_DEBUG5_VALUE_DAC2_GET(base->DEBUG5); in qeo_get_wave_output_val()
415 static inline void qeo_abz_disable_wdog(QEOV2_Type *base) in qeo_abz_disable_wdog() argument
417 base->ABZ.MODE &= ~QEOV2_ABZ_MODE_EN_WDOG_MASK; in qeo_abz_disable_wdog()
529 base->PWM.MODE |= QEOV2_PWM_MODE_ENABLE_PWM_MASK; in qeo_pwm_enable_output()
[all …]
A Dhpm_mmc_drv.h192 base->SYSCLK_FREQ = freq; in mmc_set_sysclk_freq()
195 base->SYSCLK_PERIOD = period; in mmc_set_sysclk_freq()
204 base->CR |= MMC_CR_SFTRST_MASK; in mmc_software_reset()
205 base->CR &= ~MMC_CR_SFTRST_MASK; in mmc_software_reset()
214 base->CR |= MMC_CR_MOD_EN_MASK; in mmc_enable_module()
223 base->CR &= ~MMC_CR_MOD_EN_MASK; in mmc_disable_module()
275 base->INT_EN = int_mask; in mmc_track_enable_interrupt()
285 base->INT_EN &= ~int_mask; in mmc_track_disable_interrupt()
295 return base->STA; in mmc_track_get_status()
305 base->STA = clr_mask; /* W1C */ in mmc_track_clear_status()
[all …]
A Dhpm_qeo_drv.h144 …base->WAVE.MODE = (base->WAVE.MODE & ~QEO_WAVE_MODE_WAVES_OUTPUT_TYPE_MASK) | QEO_WAVE_MODE_WAVES_… in qeo_wave_set_output_type()
155 base->WAVE.MODE &= ~QEO_WAVE_MODE_SADDLE_TYPE_MASK; in qeo_wave_set_saddle_type()
157 base->WAVE.MODE |= QEO_WAVE_MODE_SADDLE_TYPE_MASK; in qeo_wave_set_saddle_type()
204 static inline void qeo_wave_load_vd_vq(QEO_Type *base) in qeo_wave_load_vd_vq() argument
206 base->WAVE.VD_VQ_LOAD = QEO_WAVE_VD_VQ_LOAD_LOAD_MASK; in qeo_wave_load_vd_vq()
288 return QEO_DEBUG0_WAVE0_GET(base->DEBUG0); in qeo_get_wave_output_val()
290 return QEO_DEBUG0_WAVE1_GET(base->DEBUG0); in qeo_get_wave_output_val()
292 return QEO_DEBUG1_WAVE2_GET(base->DEBUG1); in qeo_get_wave_output_val()
357 static inline void qeo_abz_disable_wdog(QEO_Type *base) in qeo_abz_disable_wdog() argument
359 base->ABZ.MODE &= ~QEO_ABZ_MODE_EN_WDOG_MASK; in qeo_abz_disable_wdog()
[all …]
A Dhpm_sdxc_drv.h546 SDXC_Type *base; member
565 return base->INT_STAT; in sdxc_get_interrupt_status()
597 base->INT_STAT = status_mask; in sdxc_clear_interrupt_status()
609 base->INT_STAT_EN |= mask; in sdxc_enable_interrupt_status()
611 base->INT_STAT_EN &= ~mask; in sdxc_enable_interrupt_status()
645 return base->ADMA_ERR_STAT; in sdxc_get_adma_error_status()
852 return base->PSTATE; in sdxc_get_present_status()
884 return base->BUF_DATA; in sdxc_read_data()
894 base->BUF_DATA = data; in sdxc_write_data()
983 base->FORCE_EVENT = mask; in sdxc_force_event()
[all …]
/bsp/rv32m1_vega/rv32m1_sdk_riscv/sdmmc_2.1.2/inc/
A Dfsl_host.h125 #define GET_HOST_STATUS(base) (SDHC_GetPresentStatusFlags(base)) argument
128 #define HOST_SEND_CARD_ACTIVE(base, timeout) (SDHC_SetCardActive(base, timeout)) argument
142 #define HOST_ENABLE_CARD_CLOCK(base, enable) (SDHC_EnableSdClock(base, enable)) argument
278 #define GET_HOST_STATUS(base) (SDIF_GetControllerStatus(base)) argument
419 #define GET_HOST_STATUS(base) (USDHC_GetPresentStatusFlags(base)) argument
422 #define HOST_FORCE_SDCLOCK_ON(base, enable) (USDHC_ForceClockOn(base, enable)) argument
448 #define HOST_CHECK_TUNING_ERROR(base) (USDHC_CheckTuningError(base)) argument
457 #define HOST_ENABLE_DDR_MODE(base, flag) (USDHC_EnableDDRMode(base, flag, 1U)) argument
460 #define HOST_ENABLE_HS400_MODE(base, flag) (USDHC_EnableHS400Mode(base, flag)) argument
461 #define HOST_RESET_STROBE_DLL(base) (USDHC_ResetStrobeDLL(base)) argument
[all …]
/bsp/hpmicro/libraries/hpm_sdk/drivers/src/
A Dhpm_mmc_drv.c28 (void) base; in mmc_track_get_default_mode_config()
61 (void) base; in mmc_get_default_pos_or_delta_pos_para()
77 base->INI_SPEED = speed; in mmc_track_config_pos_para()
78 base->INI_ACCEL = accel; in mmc_track_config_pos_para()
94 base->INI_DELTA_SPEED = speed; in mmc_track_config_delta_para()
95 base->INI_DELTA_ACCEL = accel; in mmc_track_config_delta_para()
112 base->INI_PCOEF = coef_p; in mmc_track_config_coef_para()
113 base->INI_ICOEF = coef_i; in mmc_track_config_coef_para()
114 base->INI_ACOEF = coef_a; in mmc_track_config_coef_para()
169 (void) base; in mmc_pred_get_default_mode_config()
[all …]
A Dhpm_mtg_drv.c47 para->rev = base->TRA[tra_index].LOCK_REV; in mtg_get_tra_lock_result()
48 para->pos = base->TRA[tra_index].LOCK_POS; in mtg_get_tra_lock_result()
49 para->vel = base->TRA[tra_index].LOCK_VEL; in mtg_get_tra_lock_result()
50 para->acc = base->TRA[tra_index].LOCK_ACC; in mtg_get_tra_lock_result()
89 base->EVENT[event_index].CONTROL = tmp; in mtg_setup_event()
232 base->FILTER_GAIN = param->filter_gain; in mtg_setup_filter()
259 base->FILTER_CONTROL &= ~mask; in mtg_setup_filter()
260 base->FILTER_CONTROL |= tmp; in mtg_setup_filter()
329 void mtg_soft_event_trigger(MTG_Type *base) in mtg_soft_event_trigger() argument
331 base->SW_EVENT = 1; in mtg_soft_event_trigger()
[all …]
A Dhpm_sdxc_drv.c349 base->CMD_XFER = cmd_xfer; in sdxc_send_command()
498 sdxc_enable_tm_clock(base); in sdxc_init()
501 base->PROT_CTRL = prot_ctrl; in sdxc_init()
516 base->INT_SIGNAL_EN = 0UL; in sdxc_init()
606 base->SYS_CTRL = sys_ctl; in sdxc_set_dma_config()
770 base->PROT_CTRL = in sdxc_select_voltage()
804 base->PROT_CTRL = host_ctrl; in sdxc_set_data_bus_width()
828 base->AC_HOST_CTRL = in sdxc_set_speed_mode()
985 sdxc_execute_tuning(base); in sdxc_perform_tuning_flow_sequence()
996 base->SDMASA = 1; in sdxc_perform_tuning_flow_sequence()
[all …]
/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/
A Dhpm_sdxc_soc_drv.h19 static inline void sdxc_enable_tm_clock(SDXC_Type *base) in sdxc_enable_tm_clock() argument
21 base->MISC_CTRL0 |= SDXC_MISC_CTRL0_TMCLK_EN_MASK; in sdxc_enable_tm_clock()
26 base->MISC_CTRL0 |= SDXC_MISC_CTRL0_FREQ_SEL_SW_EN_MASK; in sdxc_enable_freq_selection()
41 base->MISC_CTRL0 = in sdxc_set_clock_divider()
59 static inline void sdxc_wait_card_active(SDXC_Type *base) in sdxc_wait_card_active() argument
61 base->SYS_CTRL |= SDXC_SYS_CTRL_SD_CLK_EN_MASK; in sdxc_wait_card_active()
115 base->MISC_CTRL1 = (base->MISC_CTRL1 & ~SDXC_MISC_CTRL1_CARDCLK_DLYSEL_MASK) | in sdxc_set_cardclk_delay_chain()
126 base->MISC_CTRL1 = (base->MISC_CTRL1 & ~SDXC_MISC_CTRL1_STROBE_DLYSEL_MASK) | in sdxc_set_data_strobe_delay()
132 (void) base; in sdxc_get_default_strobe_delay()
142 (void) base; in sdxc_get_default_cardclk_delay_chain()
[all …]
/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/
A Dhpm_sdxc_soc_drv.h19 static inline void sdxc_enable_tm_clock(SDXC_Type *base) in sdxc_enable_tm_clock() argument
21 base->MISC_CTRL0 |= SDXC_MISC_CTRL0_TMCLK_EN_MASK; in sdxc_enable_tm_clock()
24 static inline void sdxc_enable_freq_selection(SDXC_Type *base) in sdxc_enable_freq_selection() argument
26 base->MISC_CTRL0 |= SDXC_MISC_CTRL0_FREQ_SEL_SW_EN_MASK; in sdxc_enable_freq_selection()
36 base->MISC_CTRL0 = in sdxc_set_clock_divider()
49 static inline void sdxc_wait_card_active(SDXC_Type *base) in sdxc_wait_card_active() argument
51 base->SYS_CTRL |= SDXC_SYS_CTRL_SD_CLK_EN_MASK; in sdxc_wait_card_active()
53 base->MISC_CTRL1 |= SDXC_MISC_CTRL1_CARD_ACTIVE_MASK; in sdxc_wait_card_active()
102 (void) base; in sdxc_get_default_strobe_delay()
108 (void) base; in sdxc_get_default_cardclk_delay_chain()
[all …]

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