| /bsp/ft2004/libraries/bsp/ft_sd/ |
| A D | ft_sdctrl.c | 73 Ft_out32(pConfig->baseAddress + SD_SEN_REG_OFFSET, 0); in FsdCtrl_Init()
84 Ft_out32(pConfig->baseAddress + BD_ISR_REG, 0); in FsdCtrl_Init()
90 Ft_out32(pConfig->baseAddress + SD_DRV_REG_OFFSET, 0); in FsdCtrl_Init()
112 status = Ft_in32(pConfig->baseAddress + STATUS_REG); in FSdCtrl_CardDetect()
179 Ft_out32(pConfig->baseAddress + BLK_CNT_REG, blkNum); in FSdCtrl_WriteData()
183 Ft_out32(pConfig->baseAddress + DAT_IN_M_TX_BD, 0); in FSdCtrl_WriteData()
185 Ft_out32(pConfig->baseAddress + DAT_IN_M_TX_BD, 0); in FSdCtrl_WriteData()
206 Ft_out32(pConfig->baseAddress + BLK_CNT_REG, blkNum); in FSdCtrl_ReadData()
211 Ft_out32(pConfig->baseAddress + DAT_IN_M_RX_BD, 0); in FSdCtrl_ReadData()
213 Ft_out32(pConfig->baseAddress + DAT_IN_M_RX_BD, 0); in FSdCtrl_ReadData()
[all …]
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| A D | ft_sdctrl_intr.c | 44 Ft_out32(pConfig->baseAddress + NORMAL_INT_STATUS_REG, NORMAL_INT_STATUS_ALL_MASK); in FSdCtrl_NormalIrq()
45 Ft_out32(pConfig->baseAddress + NORMAL_INT_STATUS_REG, 0); in FSdCtrl_NormalIrq()
62 Ft_out32(pConfig->baseAddress + BD_ISR_REG, BD_ISR_ALL_MASK); in FSdCtrl_DmaIrq()
63 Ft_out32(pConfig->baseAddress + BD_ISR_REG, 0); in FSdCtrl_DmaIrq()
80 Ft_out32(pConfig->baseAddress + ERROR_INT_STATUS_REG, ERROR_INT_STATUS_ALL_MASK); in FSdCtrl_ErrIrq()
81 Ft_out32(pConfig->baseAddress + ERROR_INT_STATUS_REG, 0); in FSdCtrl_ErrIrq()
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| A D | ft_sdctrl_hw.c | 29 Ft_setBit32(pConfig->baseAddress + SOFTWARE_RESET_REG_OFFSET, SOFTWARE_RESET_SRST); in FSdCtrl_Reset()
32 Ft_clearBit32(pConfig->baseAddress + SOFTWARE_RESET_REG_OFFSET, SOFTWARE_RESET_SRST); in FSdCtrl_Reset()
35 while ((!(Ft_in32(pConfig->baseAddress + STATUS_REG) & STATUS_REG_DLSL(1)))) in FSdCtrl_Reset()
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| A D | ft_sdctrl_option.c | 32 Ft_out32(pConfig->baseAddress + NORMAL_INT_EN_REG_OFFSET, regValue); in FSdCtrl_NormalIrqSet()
45 Ft_out32(pConfig->baseAddress + ERROR_INT_EN_REG_OFFSET, regValue); in FsdCtrl_errorIrqSet()
60 Ft_out32(pConfig->baseAddress + BD_ISR_EN_REG_OFFSET, regValue); in FSdCtrl_BdIrqSet()
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| A D | ft_sdctrl_g.c | 22 .baseAddress = FT_SDC_BASEADDR,
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| A D | ft_sdctrl.h | 131 u32 baseAddress; /* Base address of the device */ member
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| /bsp/ft2004/libraries/bsp/ft_qspi/ |
| A D | ft_qspi.c | 86 Ft_out32(pConfig->baseAddress + FT_REG_QSPI_LD_PORT_OFFSET, val); in FQSpi_MemcpyToReg()
112 val = Ft_in32(pConfig->baseAddress + FT_REG_QSPI_LD_PORT_OFFSET); in FQSpi_MemcpyFromReg()
154 Ft_out32(pConfig->baseAddress + FT_REG_QSPI_RD_CFG_OFFSET, rdCfgReg.data); in FQSpi_FlashRead()
232 Ft_out32(pConfig->baseAddress + FT_REG_QSPI_FLUSH_OFFSET, 1); in FQSpi_FlashWrite()
265 Ft_out32(pConfig->baseAddress + FT_REG_QSPI_LD_PORT_OFFSET, 1); in FQSpi_FlashRegSet()
299 Ft_out32(pConfig->baseAddress + FT_REG_QSPI_ADDR_PORT_OFFSET, addr); in FQSpi_FlashRegSetWithaddr()
304 Ft_out32(pConfig->baseAddress + FT_REG_QSPI_LD_PORT_OFFSET, 0); in FQSpi_FlashRegSetWithaddr()
369 Ft_out32(pConfig->baseAddress + FT_REG_QSPI_ADDR_PORT_OFFSET, addr); in FQSpi_FlashRegGetWithAddr()
454 Ft_out32(pConfig->baseAddress + FT_REG_QSPI_FLUSH_OFFSET, 1); in FQSpi_Write()
576 Ft_out32(pConfig->baseAddress + FT_REG_QSPI_LD_PORT_OFFSET, 0); in FQSpi_CmdOperation()
[all …]
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| A D | qspi_g.c | 19 .baseAddress = FT_QSPI_BASEADDR, /* Base address of qspi */
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| A D | qspi_hw.c | 23 Ft_out32(pConfig->baseAddress + FT_REG_QSPI_CAP_OFFSET, in FQSpi_Reset()
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| A D | ft_qspi.h | 103 uintptr_t baseAddress; /* Base address of qspi */ member
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| /bsp/frdm-k64f/board/ |
| A D | drv_uart.c | 20 UART_Type *baseAddress; member
45 uart_reg = ((struct k64_serial_device *)serial->parent.user_data)->baseAddress; in _configure()
164 uart_reg = ((struct k64_serial_device *)serial->parent.user_data)->baseAddress; in _control()
200 uart_reg = ((struct k64_serial_device *)serial->parent.user_data)->baseAddress; in _putc()
210 uart_reg = ((struct k64_serial_device *)serial->parent.user_data)->baseAddress; in _getc()
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| /bsp/efm32/Libraries/emlib/src/ |
| A D | em_mpu.c | 99 EFM_ASSERT(!(init->baseAddress & ~MPU_RBAR_ADDR_Msk)); in MPU_ConfigureRegion()
102 MPU->RBAR = init->baseAddress; in MPU_ConfigureRegion()
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| /bsp/rv32m1_vega/rv32m1_sdk_riscv/devices/RV32M1/drivers/ |
| A D | fsl_xrdc.c | 201 config->baseAddress = 0U; in XRDC_GetMemAccessDefaultConfig()
228 assert(!(config->baseAddress & ((1U << (config->size + 1U)) - 1U))); in XRDC_SetMemAccessConfig()
236 base->MRGD[index].MRGD_W[0] = config->baseAddress; in XRDC_SetMemAccessConfig()
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| /bsp/efm32/Libraries/emlib/inc/ |
| A D | em_mpu.h | 129 uint32_t baseAddress; /**< Region baseaddress. */ member
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| /bsp/Infineon/psoc6-cy8ckit-062-WIFI-BT/libs/TARGET_CY8CKIT-062-WIFI-BT/config/GeneratedSource/ |
| A D | cycfg_qspi_memslot.c | 430 .baseAddress = 0x18000000U,
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| /bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/config/GeneratedSource/ |
| A D | cycfg_qspi_memslot.c | 430 .baseAddress = 0x18000000U,
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| /bsp/Infineon/psoc6-cy8ckit-062s4/libs/TARGET_CY8CKIT-062S4/config/GeneratedSource/ |
| A D | cycfg_qspi_memslot.c | 430 .baseAddress = 0x18000000U,
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| /bsp/Infineon/psoc6-evaluationkit-062S2/libs/TARGET_RTT-062S2/config/GeneratedSource/ |
| A D | cycfg_qspi_memslot.c | 452 .baseAddress = 0x18000000U,
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| /bsp/Infineon/libraries/templates/XMC7200D/libs/TARGET_APP_KIT_XMC72_EVK/config/GeneratedSource/ |
| A D | cycfg_qspi_memslot.c | 452 .baseAddress = 0x60000000U,
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| /bsp/Infineon/libraries/templates/PSOC62/libs/TARGET_CY8CKIT-062S2-43012/config/GeneratedSource/ |
| A D | cycfg_qspi_memslot.c | 430 .baseAddress = 0x18000000U,
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| /bsp/Infineon/psoc6-cy8ckit-062-BLE/libs/TARGET_CY8CKIT-062-BLE/config/GeneratedSource/ |
| A D | cycfg_qspi_memslot.c | 430 .baseAddress = 0x18000000U,
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| /bsp/Infineon/psoc6-cy8cproto-062S3-4343W/libs/TARGET_CY8CPROTO-062S3-4343W/config/GeneratedSource/ |
| A D | cycfg_qspi_memslot.c | 430 .baseAddress = 0x18000000U,
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| /bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/config/GeneratedSource/ |
| A D | cycfg_qspi_memslot.c | 452 .baseAddress = 0x60000000U,
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| /bsp/Infineon/xmc7200-kit_xmc7200_evk/libs/TARGET_APP_KIT_XMC72_EVK/config/GeneratedSource/ |
| A D | cycfg_qspi_memslot.c | 452 .baseAddress = 0x60000000U,
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| /bsp/apm32/libraries/APM32E10x_Library/APM32E10x_StdPeriphDriver/inc/ |
| A D | apm32e10x_tmr.h | 575 void TMR_ConfigDMA(TMR_T* tmr, TMR_DMA_BASE_T baseAddress, TMR_DMA_BURSTLENGTH_T burstLength);
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