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Searched refs:base_addr (Results 1 – 25 of 37) sorted by relevance

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/bsp/allwinner/libraries/sunxi-hal/hal/source/twi/
A Dhal_twi.c89 const unsigned long base_addr = twi->base_addr; in twi_clk_write_reg() local
338 twi_set_start(base_addr); in twi_start()
354 twi_set_start(base_addr); in twi_restart()
371 twi_set_stop(base_addr); in twi_stop()
504 if (twi_get_sda(base_addr)) in twi_send_clk_9pulse()
981 const uint32_t base_addr = twi->base_addr; in twi_dma_write() local
992 twi_start_xfer(base_addr); in twi_dma_write()
1054 const uint32_t base_addr = twi->base_addr; in twi_dma_read() local
1080 twi_start_xfer(base_addr); in twi_dma_read()
1221 const uint32_t base_addr = twi->base_addr; in hal_twi_core_process() local
[all …]
/bsp/allwinner/libraries/sunxi-hal/hal/source/ledc/
A Dhal_ledc.c14 static unsigned long base_addr = LEDC_BASE; variable
241 reg_val = hal_readl(base_addr + LEDC_CTRL_REG); in ledc_set_length()
244 hal_writel(reg_val, base_addr + LEDC_CTRL_REG); in ledc_set_length()
276 reg_val = hal_readl(base_addr + LEDC_CTRL_REG); in ledc_set_output_mode()
279 hal_writel(reg_val, base_addr + LEDC_CTRL_REG); in ledc_set_output_mode()
286 reg_val = hal_readl(base_addr + LEDC_INTC_REG); in ledc_disable_irq()
288 hal_writel(reg_val, base_addr + LEDC_INTC_REG); in ledc_disable_irq()
295 reg_val = hal_readl(base_addr + LEDC_INTC_REG); in ledc_enable_irq()
297 hal_writel(reg_val, base_addr + LEDC_INTC_REG); in ledc_enable_irq()
327 return hal_readl(base_addr + LEDC_INTS_REG); in ledc_get_irq_status()
[all …]
/bsp/cvitek/drivers/
A Ddrv_gpio.c67 rt_ubase_t base_addr; in dwapb_toggle_trigger() local
72 pol = dwapb_read32(base_addr + GPIO_INT_POLARITY); in dwapb_toggle_trigger()
81 dwapb_write32(base_addr + GPIO_INT_POLARITY, pol); in dwapb_toggle_trigger()
87 rt_ubase_t base_addr; in dwapb_pin_mode() local
111 rt_ubase_t base_addr; in dwapb_pin_write() local
126 rt_ubase_t base_addr; in dwapb_pin_read() local
175 rt_ubase_t base_addr; in dwapb_pin_attach_irq() local
241 rt_ubase_t base_addr; in dwapb_pin_irq_enable() local
249 dwapb_write32(base_addr + GPIO_INTEN, reg_val); in dwapb_pin_irq_enable()
268 rt_ubase_t base_addr; in rt_hw_gpio_isr() local
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/bsp/allwinner/libraries/sunxi-hal/hal/source/lradc/
A Dhal_lradc.c38 static uint32_t base_addr = LRADC_BASE; variable
49 reg_val = hal_readl(base_addr + LRADC_CTRL_REG); in lradc_ctrl_set()
51 hal_writel(reg_val, base_addr + LRADC_CTRL_REG); in lradc_ctrl_set()
58 reg_val = hal_readl(base_addr + LRADC_CTRL_REG); in lradc_ctrl_reset()
60 hal_writel(reg_val, base_addr + LRADC_CTRL_REG); in lradc_ctrl_reset()
67 reg_val = hal_readl(base_addr + LRADC_INTC_REG); in lradc_irq_set()
69 hal_writel(reg_val, base_addr + LRADC_INTC_REG); in lradc_irq_set()
76 reg_val = hal_readl(base_addr + LRADC_INTC_REG); in lradc_irq_reset()
78 hal_writel(reg_val, base_addr + LRADC_INTC_REG); in lradc_irq_reset()
93 uint32_t reg_val = hal_readl(base_addr + LRADC_DATA0_REG); in lradc_irq_handler()
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/bsp/hifive1/freedom-e-sdk/bsp/drivers/plic/
A Dplic_driver.c23 uintptr_t base_addr, in PLIC_init() argument
29 this_plic->base_addr = base_addr; in PLIC_init()
35 volatile_memzero((uint8_t*) (this_plic->base_addr + in PLIC_init()
41 volatile_memzero ((uint8_t *)(this_plic->base_addr + in PLIC_init()
47 (this_plic->base_addr + in PLIC_init()
59 volatile plic_threshold* threshold_ptr = (plic_threshold*) (this_plic->base_addr + in PLIC_set_threshold()
71 volatile uint8_t * current_ptr = (volatile uint8_t *)(this_plic->base_addr + in PLIC_enable_interrupt()
84 volatile uint8_t * current_ptr = (volatile uint8_t *) (this_plic->base_addr + in PLIC_disable_interrupt()
98 (this_plic->base_addr + in PLIC_set_priority()
110 (this_plic->base_addr + in PLIC_claim_interrupt()
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A Dplic_driver.h13 uintptr_t base_addr; member
26 uintptr_t base_addr,
/bsp/sparkfun-redv/freedom-e-sdk/bsp/drivers/plic/
A Dplic_driver.c23 uintptr_t base_addr, in PLIC_init() argument
29 this_plic->base_addr = base_addr; in PLIC_init()
35 volatile_memzero((uint8_t*) (this_plic->base_addr + in PLIC_init()
41 volatile_memzero ((uint8_t *)(this_plic->base_addr + in PLIC_init()
47 (this_plic->base_addr + in PLIC_init()
59 volatile plic_threshold* threshold_ptr = (plic_threshold*) (this_plic->base_addr + in PLIC_set_threshold()
71 volatile uint8_t * current_ptr = (volatile uint8_t *)(this_plic->base_addr + in PLIC_enable_interrupt()
84 volatile uint8_t * current_ptr = (volatile uint8_t *) (this_plic->base_addr + in PLIC_disable_interrupt()
98 (this_plic->base_addr + in PLIC_set_priority()
110 (this_plic->base_addr + in PLIC_claim_interrupt()
[all …]
A Dplic_driver.h13 uintptr_t base_addr; member
26 uintptr_t base_addr,
/bsp/nxp/imx/imx6ull-smart/drivers/
A Ddrv_eth.c220 ENET_Type *base_addr = RT_NULL; in rt_imx6ul_eth_init() local
227 base_addr = imx6ul_device->enet_virtual_base_addr; in rt_imx6ul_eth_init()
266 ENET_ActiveRead(base_addr); in rt_imx6ul_eth_init()
331 ENET_Type *base_addr = RT_NULL; in read_data_from_eth() local
336 base_addr = imx6ul_device->enet_virtual_base_addr; in read_data_from_eth()
344 ENET_EnableInterrupts(base_addr,ENET_RX_INTERRUPT); in read_data_from_eth()
349 ENET_ActiveRead(base_addr); in read_data_from_eth()
369 ENET_Type *base_addr = RT_NULL; in rt_imx6ul_eth_tx() local
372 base_addr = imx6ul_device->enet_virtual_base_addr; in rt_imx6ul_eth_tx()
481 ENET_Type *base_addr = RT_NULL; in phy_detect_thread_entry() local
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/bsp/nuvoton/libraries/nuc980/rtt_port/
A Ddrv_pwm.c49 uint32_t base_addr; member
61 .base_addr = PWM0_BA,
70 .base_addr = PWM1_BA,
93 uint32_t u32RegAdrrPCR = psNuPWM->base_addr + 0x8; in nu_pwm_enable()
101 uint32_t u32RegAdrrPCR = psNuPWM->base_addr + 0x8; in nu_pwm_enable()
113 uint32_t u32RegAdrrPPR = psNuPWM->base_addr; in nu_pwm_get()
114 uint32_t u32RegAdrrCSR = psNuPWM->base_addr + 0x04; in nu_pwm_get()
115 uint32_t u32RegAdrrCNR = psNuPWM->base_addr + 0xC + (config->channel * 0xC); in nu_pwm_get()
116 uint32_t u32RegAdrrCMR = psNuPWM->base_addr + 0x10 + (config->channel * 0xC); in nu_pwm_get()
248 nu_pwm_config(psNuPWM->base_addr, config->channel, u32FreqInHz, u32PulseInHz); in nu_pwm_set()
/bsp/nuvoton/libraries/n9h30/rtt_port/
A Ddrv_pwm.c46 uint32_t base_addr; member
58 .base_addr = PWM_BA,
82 uint32_t u32RegAdrrPCR = psNuPWM->base_addr + 0x8; in nu_pwm_enable()
90 uint32_t u32RegAdrrPCR = psNuPWM->base_addr + 0x8; in nu_pwm_enable()
102 uint32_t u32RegAdrrPPR = psNuPWM->base_addr; in nu_pwm_get()
103 uint32_t u32RegAdrrCSR = psNuPWM->base_addr + 0x04; in nu_pwm_get()
104 uint32_t u32RegAdrrCNR = psNuPWM->base_addr + 0xC + (config->channel * 0xC); in nu_pwm_get()
105 uint32_t u32RegAdrrCMR = psNuPWM->base_addr + 0x10 + (config->channel * 0xC); in nu_pwm_get()
237 nu_pwm_config(psNuPWM->base_addr, config->channel, u32FreqInHz, u32PulseInHz); in nu_pwm_set()
/bsp/phytium/libraries/drivers/
A Ddrv_spi.c56 uintptr base_addr = config_p->base_addr; in FSpimSetupInterrupt() local
71 FSpimMaskIrq(base_addr, FSPIM_IMR_ALL_BITS); in FSpimSetupInterrupt()
215 input_cfg.base_addr = (uintptr)rt_ioremap((void *)input_cfg.base_addr, 0x1000); in spi_init()
A Ddrv_gpio.c67 input_cfg.base_addr = (uintptr)rt_ioremap((void *)input_cfg.base_addr, 0x1000); in drv_pin_mode()
116 map->base_addr = (uintptr)rt_ioremap((void *)map->base_addr, 0x1000); in drv_pin_attach_irq()
A Ddrv_sdif.c464 uintptr base_addr = sdif->config.base_addr; in sdif_set_iocfg() local
511 FSdifSetBusWidth(base_addr, 1U); in sdif_set_iocfg()
514 FSdifSetBusWidth(base_addr, 4U); in sdif_set_iocfg()
517 FSdifSetBusWidth(base_addr, 8U); in sdif_set_iocfg()
529 uintptr base_addr = sdif->config.base_addr; in sdif_card_status() local
531 return FSdifCheckIfCardExists(base_addr) ? 1 : 0; in sdif_card_status()
654 sdif_config.base_addr = (uintptr)rt_ioremap((void *)sdif_config.base_addr, 0x1000); in sdif_host_init()
A Ddrv_qspi.c45 pconfig.base_addr = (uintptr)rt_ioremap((void *)pconfig.base_addr, 0x1000); in FQspiInit()
121 uintptr base_addr = pctrl->config.base_addr; in RTQspiFlashWriteData() local
189 FQspiWriteFlush(base_addr); in RTQspiFlashWriteData()
A Ddrv_can.c61 uintptr base_addr = instance_p->config.base_address; in CanErrorCallback() local
63 LOG_E("error_status is %x.", FCAN_READ_REG32(base_addr, FCAN_INTR_OFFSET)); in CanErrorCallback()
64 … LOG_E("rxerr_cnt is %x.", FCAN_ERR_CNT_RFN_GET(FCAN_READ_REG32(base_addr, FCAN_ERR_CNT_OFFSET))); in CanErrorCallback()
65 … LOG_E("txerr_cnt is %x.", FCAN_ERR_CNT_TFN_GET(FCAN_READ_REG32(base_addr, FCAN_ERR_CNT_OFFSET))); in CanErrorCallback()
/bsp/gd32/risc-v/libraries/GD32VF103_Firmware_Library/GD32VF103_usbfs_library/device/class/dfu/Source/
A Ddfu_core.c245 dfu_handler.base_addr = APP_LOADED_ADDR; in dfu_init()
357 dfu->base_addr = *(uint32_t *)(dfu->buf + 1U); in dfu_getstatus_complete()
359 dfu->base_addr = *(uint32_t *)(dfu->buf + 1U); in dfu_getstatus_complete()
361 dfu_mal_erase(dfu->base_addr); in dfu_getstatus_complete()
370 addr = (dfu->block_num - 2U) * TRANSFER_SIZE + dfu->base_addr; in dfu_getstatus_complete()
514 addr = (dfu->block_num - 2U) * TRANSFER_SIZE + dfu->base_addr; in dfu_upload()
554 dfu_mal_getstatus (dfu->base_addr, CMD_ERASE, (uint8_t *)&dfu->bwPollTimeout0); in dfu_getstatus()
556 dfu_mal_getstatus (dfu->base_addr, CMD_WRITE, (uint8_t *)&dfu->bwPollTimeout0); in dfu_getstatus()
/bsp/xuantie/libraries/xuantie_libraries/csi/csi2/include/core/
A Dcore_rv32.h639 __STATIC_INLINE void csi_mpu_config_region(uint32_t idx, uint32_t base_addr, region_size_e size, in csi_mpu_config_region() argument
654 addr = base_addr >> 2; in csi_mpu_config_region()
657 addr = base_addr >> 2; in csi_mpu_config_region()
660 addr = ((base_addr >> 2) & (0xFFFFFFFFU - ((1 << (size + 1)) - 1))) | ((1 << size) - 1); in csi_mpu_config_region()
952 __STATIC_INLINE void csi_sysmap_config_region(uint32_t idx, uint32_t base_addr, uint32_t attr) in csi_sysmap_config_region() argument
960 addr = base_addr >> 12; in csi_sysmap_config_region()
1398 __STATIC_INLINE void csi_itcm_set_base_addr(unsigned long base_addr) in csi_itcm_set_base_addr() argument
1400 …__set_MITCMCR((__get_MITCMCR() & (~MITCMCR_Base_Address_Msk)) | (base_addr & MITCMCR_Base_Address_… in csi_itcm_set_base_addr()
1408 __STATIC_INLINE void csi_dtcm_set_base_addr(unsigned long base_addr) in csi_dtcm_set_base_addr() argument
1410 …__set_MDTCMCR((__get_MDTCMCR() & (~MDTCMCR_Base_Address_Msk)) | (base_addr & MDTCMCR_Base_Address_… in csi_dtcm_set_base_addr()
A Dcore_rv64.h988 __STATIC_INLINE void csi_mpu_config_region(uint32_t idx, uint32_t base_addr, region_size_e size, in csi_mpu_config_region() argument
1003 addr = base_addr >> 2; in csi_mpu_config_region()
1006 addr = base_addr >> 2; in csi_mpu_config_region()
1009 addr = ((base_addr >> 2) & (0xFFFFFFFFU - ((1 << (size + 1)) - 1))) | ((1 << size) - 1); in csi_mpu_config_region()
1624 __STATIC_INLINE void csi_fpp_set_base_addr(unsigned long base_addr) in csi_fpp_set_base_addr() argument
1627 | ((base_addr << MFPPCR_Base_Address_Pos) & MFPPCR_Base_Address_Msk)); in csi_fpp_set_base_addr()
1881 __STATIC_INLINE void csi_itcm_set_base_addr(unsigned long base_addr) in csi_itcm_set_base_addr() argument
1883 …__set_MITCMCR((__get_MITCMCR() & (~MITCMCR_Base_Address_Msk)) | (base_addr << MITCMCR_Base_Address… in csi_itcm_set_base_addr()
1891 __STATIC_INLINE void csi_dtcm_set_base_addr(unsigned long base_addr) in csi_dtcm_set_base_addr() argument
1893 …__set_MDTCMCR((__get_MDTCMCR() & (~MDTCMCR_Base_Address_Msk)) | (base_addr << MDTCMCR_Base_Address… in csi_dtcm_set_base_addr()
/bsp/xuantie/libraries/xuantie_libraries/csi/csi2/include/drv/
A Dsasc.h100 csi_error_t csi_sasc_ram_config(uint8_t region_id, uint32_t base_addr, csi_sasc_ram_size_t size, cs…
110 csi_error_t csi_sasc_flash_config(uint8_t region_id, uint32_t base_addr, csi_sasc_flash_size_t size…
/bsp/allwinner/libraries/sunxi-hal/hal/source/g2d_rcq/
A Dg2d_rotate.c53 static unsigned long base_addr; variable
72 #define read_bvalue(offset) get_bvalue(base_addr + offset)
74 #define write_bvalue(offset, value) put_bvalue(base_addr + offset, value)
76 #define read_hvalue(offset) get_hvalue(base_addr + offset)
78 #define write_hvalue(offset, value) put_hvalue(base_addr + offset, value)
80 #define read_wvalue(offset) get_wvalue(base_addr + offset)
82 #define write_wvalue(offset, value) put_wvalue(base_addr + offset, value)
86 base_addr = base; in g2d_rot_set_base()
/bsp/thead-smart/drivers/
A Dcore_rv32.h618 __STATIC_INLINE void csi_mpu_config_region(uint32_t idx, uint32_t base_addr, region_size_e size, in csi_mpu_config_region() argument
633 addr = base_addr >> 2; in csi_mpu_config_region()
636 addr = base_addr >> 2; in csi_mpu_config_region()
639 addr = ((base_addr >> 2) & (0xFFFFFFFFU - ((1 << (size + 1)) - 1))) | ((1 << size) - 1); in csi_mpu_config_region()
835 __STATIC_INLINE void csi_sysmap_config_region(uint32_t idx, uint32_t base_addr, uint32_t attr) in csi_sysmap_config_region() argument
843 addr = base_addr >> 12; in csi_sysmap_config_region()
/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/arch/risc-v/t-head/Core/Include/
A Dcore_rv32.h623 __STATIC_INLINE void csi_mpu_config_region(uint32_t idx, uint32_t base_addr, region_size_e size, in csi_mpu_config_region() argument
638 addr = base_addr >> 2; in csi_mpu_config_region()
641 addr = base_addr >> 2; in csi_mpu_config_region()
644 addr = ((base_addr >> 2) & (0xFFFFFFFFU - ((1 << (size + 1)) - 1))) | ((1 << size) - 1); in csi_mpu_config_region()
940 __STATIC_INLINE void csi_sysmap_config_region(uint32_t idx, uint32_t base_addr, uint32_t attr) in csi_sysmap_config_region() argument
948 addr = base_addr >> 12; in csi_sysmap_config_region()
/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/platform/
A DEif_flash.c11 uint32_t base_addr; member
/bsp/essemi/es32vf2264/libraries/RV_CORE/Include/
A Dcore_rv32.h579 __STATIC_INLINE void csi_mpu_config_region(uint32_t idx, uint32_t base_addr, region_size_e size, in csi_mpu_config_region() argument
594 addr = base_addr >> 2; in csi_mpu_config_region()
597 addr = base_addr >> 2; in csi_mpu_config_region()
600 addr = ((base_addr >> 2) & (0xFFFFFFFFU - ((1 << (size + 1)) - 1))) | ((1 << size) - 1); in csi_mpu_config_region()

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