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/bsp/ti/c28x/libraries/tms320f28379d/common/source/
A DF2837xD_Mcbsp.c89 McbspaRegs.SPCR2.bit.FRST = 0; in InitMcbspa()
90 McbspaRegs.SPCR2.bit.GRST = 0; in InitMcbspa()
91 McbspaRegs.SPCR2.bit.XRST = 0; in InitMcbspa()
92 McbspaRegs.SPCR1.bit.RRST = 0; in InitMcbspa()
119 McbspaRegs.SRGR2.bit.FSGM = 1; in InitMcbspa()
125 McbspaRegs.PCR.bit.SCLKME = 0; in InitMcbspa()
133 McbspaRegs.SRGR1.bit.FWID = 1; in InitMcbspa()
140 McbspaRegs.PCR.bit.CLKXM = 1; in InitMcbspa()
141 McbspaRegs.PCR.bit.FSXM = 1; in InitMcbspa()
147 McbspaRegs.SPCR2.bit.GRST = 1; in InitMcbspa()
[all …]
A DF2837xD_SysCtrl.c193 CpuSysRegs.PCLKCR0.bit.CLA1 = 1; in InitPeripheralClocks()
194 CpuSysRegs.PCLKCR0.bit.DMA = 1; in InitPeripheralClocks()
200 CpuSysRegs.PCLKCR0.bit.HRPWM = 1; in InitPeripheralClocks()
234 CpuSysRegs.PCLKCR6.bit.SD1 = 1; in InitPeripheralClocks()
235 CpuSysRegs.PCLKCR6.bit.SD2 = 1; in InitPeripheralClocks()
653 WdRegs.WDKEY.bit.WDKEY = 0x55; in InitSysPll()
654 WdRegs.WDKEY.bit.WDKEY = 0xAA; in InitSysPll()
800 while((CpuTimer2Regs.TCR.bit.TIF == 0) && (CpuTimer1Regs.TCR.bit.TIF == 0)); in InitSysPll()
847 WdRegs.WDKEY.bit.WDKEY = 0x55; in InitSysPll()
848 WdRegs.WDKEY.bit.WDKEY = 0xAA; in InitSysPll()
[all …]
A DF2837xD_Upp.c100 GpioCtrlRegs.GPAGMUX1.bit.GPIO13 = 3; // Configure GPIO13 as uPP_D7 in InitUpp1Gpio()
113 GpioCtrlRegs.GPAMUX1.bit.GPIO13 = 3; // Configure GPIO13 as uPP_D7 in InitUpp1Gpio()
114 GpioCtrlRegs.GPAMUX1.bit.GPIO14 = 3; // Configure GPIO14 as uPP_D6 in InitUpp1Gpio()
115 GpioCtrlRegs.GPAMUX1.bit.GPIO15 = 3; // Configure GPIO15 as uPP_D5 in InitUpp1Gpio()
116 GpioCtrlRegs.GPAMUX2.bit.GPIO16 = 3; // Configure GPIO16 as uPP_D4 in InitUpp1Gpio()
117 GpioCtrlRegs.GPAMUX2.bit.GPIO17 = 3; // Configure GPIO17 as uPP_D3 in InitUpp1Gpio()
118 GpioCtrlRegs.GPAMUX2.bit.GPIO18 = 3; // Configure GPIO18 as uPP_D2 in InitUpp1Gpio()
119 GpioCtrlRegs.GPAMUX2.bit.GPIO19 = 3; // Configure GPIO19 as uPP_D1 in InitUpp1Gpio()
120 GpioCtrlRegs.GPAMUX2.bit.GPIO20 = 3; // Configure GPIO20 as uPP_D0 in InitUpp1Gpio()
131 UppRegs.PERCTL.bit.SOFTRST = 1; // Issue uPP Internal Reset. in SoftResetUpp()
[all …]
A DF2837xD_EPwm.c92 GpioCtrlRegs.GPAMUX1.bit.GPIO0 = 1; // Configure GPIO0 as EPWM1A in InitEPwm1Gpio()
93 GpioCtrlRegs.GPAMUX1.bit.GPIO1 = 1; // Configure GPIO1 as EPWM1B in InitEPwm1Gpio()
124 GpioCtrlRegs.GPAMUX1.bit.GPIO2 = 1; // Configure GPIO2 as EPWM2A in InitEPwm2Gpio()
125 GpioCtrlRegs.GPAMUX1.bit.GPIO3 = 1; // Configure GPIO3 as EPWM2B in InitEPwm2Gpio()
156 GpioCtrlRegs.GPAMUX1.bit.GPIO4 = 1; // Configure GPIO4 as EPWM3A in InitEPwm3Gpio()
157 GpioCtrlRegs.GPAMUX1.bit.GPIO5 = 1; // Configure GPIO5 as EPWM3B in InitEPwm3Gpio()
189 GpioCtrlRegs.GPAMUX1.bit.GPIO6 = 1; // Configure GPIO6 as EPWM4A in InitEPwm4Gpio()
190 GpioCtrlRegs.GPAMUX1.bit.GPIO7 = 1; // Configure GPIO7 as EPWM4B in InitEPwm4Gpio()
221 GpioCtrlRegs.GPAMUX1.bit.GPIO8 = 1; // Configure GPIO8 as EPWM5A in InitEPwm5Gpio()
222 GpioCtrlRegs.GPAMUX1.bit.GPIO9 = 1; // Configure GPIO9 as EPWM5B in InitEPwm5Gpio()
[all …]
A DF2837xD_EQep.c162 GpioCtrlRegs.GPAMUX2.bit.GPIO20 = 1; // Configure GPIO20 as EQEP1A in InitEQep1Gpio()
163 GpioCtrlRegs.GPAMUX2.bit.GPIO21 = 1; // Configure GPIO21 as EQEP1B in InitEQep1Gpio()
164 GpioCtrlRegs.GPAMUX2.bit.GPIO22 = 1; // Configure GPIO22 as EQEP1S in InitEQep1Gpio()
165 GpioCtrlRegs.GPAMUX2.bit.GPIO23 = 1; // Configure GPIO23 as EQEP1I in InitEQep1Gpio()
247 GpioCtrlRegs.GPAMUX2.bit.GPIO24 = 2; // Configure GPIO24 as EQEP2A in InitEQep2Gpio()
248 GpioCtrlRegs.GPAMUX2.bit.GPIO25 = 2; // Configure GPIO25 as EQEP2B in InitEQep2Gpio()
249 GpioCtrlRegs.GPAMUX2.bit.GPIO26 = 2; // Configure GPIO26 as EQEP2S in InitEQep2Gpio()
250 GpioCtrlRegs.GPAMUX2.bit.GPIO27 = 2; // Configure GPIO27 as EQEP2I in InitEQep2Gpio()
357 GpioCtrlRegs.GPAGMUX2.bit.GPIO28 = 1; // Configure GPIO28 as EQEP3A in InitEQep3Gpio()
358 GpioCtrlRegs.GPAMUX2.bit.GPIO28 = 2; // Configure GPIO28 as EQEP3A in InitEQep3Gpio()
[all …]
A DF2837xD_I2C.c80 GpioCtrlRegs.GPAPUD.bit.GPIO0 = 0; in I2cAGpioConfig()
81 GpioCtrlRegs.GPAPUD.bit.GPIO1 = 0; in I2cAGpioConfig()
87 GpioCtrlRegs.GPAQSEL1.bit.GPIO0 = 3; in I2cAGpioConfig()
88 GpioCtrlRegs.GPAQSEL1.bit.GPIO1 = 3; in I2cAGpioConfig()
96 GpioCtrlRegs.GPAGMUX1.bit.GPIO0 = 1; in I2cAGpioConfig()
112 GpioCtrlRegs.GPBPUD.bit.GPIO32 = 0; in I2cAGpioConfig()
113 GpioCtrlRegs.GPBPUD.bit.GPIO33 = 0; in I2cAGpioConfig()
149 GpioCtrlRegs.GPCPUD.bit.GPIO91 = 0; in I2cAGpioConfig()
150 GpioCtrlRegs.GPCPUD.bit.GPIO92 = 0; in I2cAGpioConfig()
209 GpioCtrlRegs.GPAPUD.bit.GPIO2 = 0; in I2cBGpioConfig()
[all …]
A DF2837xD_sdfm_drivers.c75 (*SDFM[sdfmNumber]).SDCTLPARM1.bit.MOD = mode; in Sdfm_configureInputCtrl()
146 (*SDFM[sdfmNumber]).SDCMPH1.bit.HLT = HLT; in Sdfm_configureComparator()
147 (*SDFM[sdfmNumber]).SDCMPL1.bit.LLT = LLT; in Sdfm_configureComparator()
168 (*SDFM[sdfmNumber]).SDCMPH2.bit.HLT = HLT; in Sdfm_configureComparator()
169 (*SDFM[sdfmNumber]).SDCMPL2.bit.LLT = LLT; in Sdfm_configureComparator()
190 (*SDFM[sdfmNumber]).SDCMPH3.bit.HLT = HLT; in Sdfm_configureComparator()
191 (*SDFM[sdfmNumber]).SDCMPL3.bit.LLT = LLT; in Sdfm_configureComparator()
212 (*SDFM[sdfmNumber]).SDCMPH4.bit.HLT = HLT; in Sdfm_configureComparator()
213 (*SDFM[sdfmNumber]).SDCMPL4.bit.LLT = LLT; in Sdfm_configureComparator()
513 (*SDFM[sdfmNumber]).SDCTL.bit.MIE = 1; in Sdfm_enableMIE()
[all …]
A DF2837xD_Spi.c78 SpiaRegs.SPICCR.bit.SPISWRESET = 0; in InitSpi()
79 SpiaRegs.SPICCR.bit.CLKPOLARITY = 0; in InitSpi()
80 SpiaRegs.SPICCR.bit.SPICHAR = (16-1); in InitSpi()
81 SpiaRegs.SPICCR.bit.SPILBK = 1; in InitSpi()
87 SpiaRegs.SPICTL.bit.MASTER_SLAVE = 1; in InitSpi()
88 SpiaRegs.SPICTL.bit.TALK = 1; in InitSpi()
89 SpiaRegs.SPICTL.bit.CLK_PHASE = 0; in InitSpi()
90 SpiaRegs.SPICTL.bit.SPIINTENA = 0; in InitSpi()
93 SpiaRegs.SPIBRR.bit.SPI_BIT_RATE = SPI_BRR; in InitSpi()
97 SpiaRegs.SPIPRI.bit.FREE = 1; in InitSpi()
[all …]
A DF2837xD_Emif.c142 Emif1Regs.ASYNC_CS2_CR.bit.W_HOLD = w_hold; in ASync_cs2_config()
146 Emif1Regs.ASYNC_CS2_CR.bit.SS = strobe_sel; in ASync_cs2_config()
200 Emif1Regs.ASYNC_CS3_CR.bit.R_SETUP = r_setup; in ASync_cs3_config()
201 Emif1Regs.ASYNC_CS3_CR.bit.W_HOLD = w_hold; in ASync_cs3_config()
203 Emif1Regs.ASYNC_CS3_CR.bit.W_SETUP = w_setup; in ASync_cs3_config()
204 Emif1Regs.ASYNC_CS3_CR.bit.EW = extend_wait; in ASync_cs3_config()
205 Emif1Regs.ASYNC_CS3_CR.bit.SS = strobe_sel; in ASync_cs3_config()
233 Emif1Regs.ASYNC_CS4_CR.bit.R_SETUP = r_setup; in ASync_cs4_config()
234 Emif1Regs.ASYNC_CS4_CR.bit.W_HOLD = w_hold; in ASync_cs4_config()
237 Emif1Regs.ASYNC_CS4_CR.bit.EW = extend_wait; in ASync_cs4_config()
[all …]
A DF2837xD_Dma.c59 DmaRegs.DMACTRL.bit.HARDRESET = 1; in DMAInitialize()
65 DmaRegs.DEBUGCTRL.bit.FREE = 1; in DMAInitialize()
181 DmaRegs.CH1.MODE.bit.PERINTSEL = 1; in DMACH1ModeConfig()
200 PieCtrlRegs.PIEIER7.bit.INTx1 = 1; in DMACH1ModeConfig()
211 DmaRegs.CH1.CONTROL.bit.RUN = 1; in StartDMACH1()
345 PieCtrlRegs.PIEIER7.bit.INTx2 = 1; in DMACH2ModeConfig()
356 DmaRegs.CH2.CONTROL.bit.RUN = 1; in StartDMACH2()
500 DmaRegs.CH3.CONTROL.bit.RUN = 1; in StartDMACH3()
644 DmaRegs.CH4.CONTROL.bit.RUN = 1; in StartDMACH4()
788 DmaRegs.CH5.CONTROL.bit.RUN = 1; in StartDMACH5()
[all …]
A Dusb_hal.c73 GpioCtrlRegs.GPBAMSEL.bit.GPIO42 = 1; in USBGPIOEnable()
74 GpioCtrlRegs.GPBAMSEL.bit.GPIO43 = 1; in USBGPIOEnable()
77 GpioCtrlRegs.GPBDIR.bit.GPIO46 = 0; in USBGPIOEnable()
79 GpioCtrlRegs.GPBDIR.bit.GPIO47 = 0; in USBGPIOEnable()
81 GpioCtrlRegs.GPDGMUX2.bit.GPIO120 = 3; in USBGPIOEnable()
82 GpioCtrlRegs.GPDMUX2.bit.GPIO120 = 3; in USBGPIOEnable()
84 GpioCtrlRegs.GPDMUX2.bit.GPIO121 = 3; in USBGPIOEnable()
97 GpioCtrlRegs.GPBAMSEL.bit.GPIO42 = 0; in USBGPIODisable()
98 GpioCtrlRegs.GPBAMSEL.bit.GPIO43 = 0; in USBGPIODisable()
101 GpioCtrlRegs.GPDMUX2.bit.GPIO120 = 0; in USBGPIODisable()
[all …]
A DF2837xD_can.c61 CanaRegs.CAN_CTL.bit.Init = 1; in InitCAN()
62 CanaRegs.CAN_CTL.bit.SWR = 1; in InitCAN()
67 while(CanaRegs.CAN_IF1CMD.bit.Busy) in InitCAN()
76 CanaRegs.CAN_IF1CMD.bit.DIR = 1; in InitCAN()
77 CanaRegs.CAN_IF1CMD.bit.Arb = 1; in InitCAN()
78 CanaRegs.CAN_IF1CMD.bit.Control = 1; in InitCAN()
84 CanaRegs.CAN_IF2CMD.bit.DIR = 1; in InitCAN()
85 CanaRegs.CAN_IF2CMD.bit.Arb = 1; in InitCAN()
86 CanaRegs.CAN_IF2CMD.bit.Control = 1; in InitCAN()
100 while(CanaRegs.CAN_IF1CMD.bit.Busy) in InitCAN()
[all …]
/bsp/nv32f100x/lib/inc/
A DBME.h111 #define BME_BIT_CLEAR(ADDR,bit) (*(volatile uint32_t *)(((uint32_t)ADDR) \ argument
132 #define BME_BIT_SET(ADDR,bit) (*(volatile uint32_t *)(((uint32_t)ADDR) \ argument
155 | ((bit)<<23) | ((width-1))<<19))
187 #define BME_BIT_CLEAR(ADDR,bit) (*(volatile uint32_t *)(((uint32_t)ADDR) \
195 #define BME_BIT_SET(ADDR,bit) (*(volatile uint32_t *)(((uint32_t)ADDR) \
301 #define BME_BIT_CLEAR_8b(ADDR,bit) (*(volatile uint8_t *)(((uint32_t)ADDR) \ argument
322 #define BME_BIT_SET_8b(ADDR,bit) (*(volatile uint8_t *)(((uint32_t)ADDR) \ argument
376 #define BME_BIT_CLEAR_8b(ADDR,bit) (*(volatile uint8_t *)(((uint32_t)ADDR) \
384 #define BME_BIT_SET_8b(ADDR,bit) (*(volatile uint8_t *)(((uint32_t)ADDR) \
513 #define BME_BIT_SET_16b(ADDR,bit) (*(volatile uint16_t *)(((uint32_t)ADDR) \ argument
[all …]
/bsp/ti/c28x/libraries/HAL_Drivers/
A Ddrv_pwm.c142 epwm->CMPA.bit.CMPA = comp; in drv_pwm_set()
145 epwm->CMPB.bit.CMPB = comp; in drv_pwm_set()
150 epwm->AQCTLA.bit.CAD = AQ_SET; in drv_pwm_set()
152 epwm->AQCTLB.bit.CBD = AQ_SET; in drv_pwm_set()
156 epwm->DBCTL.bit.POLSEL = DB_ACTV_HIC; in drv_pwm_set()
157 epwm->DBRED.bit.DBRED = dead_time; in drv_pwm_set()
158 epwm->DBFED.bit.DBFED = dead_time; in drv_pwm_set()
173 epwm->DBCTL.bit.IN_MODE = DBA_ALL; in drv_pwm_set()
310 epwm->TZCLR.bit.OST = 1; in drv_pwm_enable()
317 epwm->TZFRC.bit.OST = 1; in drv_pwm_enable()
[all …]
A Ddrv_sci.c199 GpioCtrlRegs.GPBMUX1.bit.GPIO42 = 3; in rt_hw_sci_init()
200 GpioCtrlRegs.GPBMUX1.bit.GPIO43 = 3; in rt_hw_sci_init()
201 GpioCtrlRegs.GPBGMUX1.bit.GPIO42 = 3; in rt_hw_sci_init()
202 GpioCtrlRegs.GPBGMUX1.bit.GPIO43 = 3; in rt_hw_sci_init()
204 GpioCtrlRegs.GPAMUX2.bit.GPIO18 = 2; in rt_hw_sci_init()
205 GpioCtrlRegs.GPAMUX2.bit.GPIO19 = 2; in rt_hw_sci_init()
206 GpioCtrlRegs.GPAGMUX2.bit.GPIO18 = 0; in rt_hw_sci_init()
209 GpioCtrlRegs.GPBMUX2.bit.GPIO56 = 2; in rt_hw_sci_init()
214 CpuSysRegs.PCLKCR7.bit.SCI_A = 1; in rt_hw_sci_init()
215 CpuSysRegs.PCLKCR7.bit.SCI_B = 1; in rt_hw_sci_init()
[all …]
/bsp/stm32/stm32mp157a-st-ev1/board/ports/OpenAMP/libmetal/lib/include/metal/
A Dutilities.h74 #define metal_bit(bit) (1UL << (bit)) argument
105 unsigned int bit; in metal_bitmap_next_set_bit() local
106 for (bit = start; in metal_bitmap_next_set_bit()
107 bit < max && !metal_bitmap_is_bit_set(bitmap, bit); in metal_bitmap_next_set_bit()
108 bit ++) in metal_bitmap_next_set_bit()
110 return bit; in metal_bitmap_next_set_bit()
116 (bit) = metal_bitmap_next_set_bit((bitmap), (bit), (max)))
124 bit < max && !metal_bitmap_is_bit_clear(bitmap, bit); in metal_bitmap_next_clear_bit()
125 bit ++) in metal_bitmap_next_clear_bit()
127 return bit; in metal_bitmap_next_clear_bit()
[all …]
/bsp/stm32/stm32mp157a-st-discovery/board/ports/OpenAMP/libmetal/lib/include/metal/
A Dutilities.h74 #define metal_bit(bit) (1UL << (bit)) argument
105 unsigned int bit; in metal_bitmap_next_set_bit() local
106 for (bit = start; in metal_bitmap_next_set_bit()
107 bit < max && !metal_bitmap_is_bit_set(bitmap, bit); in metal_bitmap_next_set_bit()
108 bit ++) in metal_bitmap_next_set_bit()
110 return bit; in metal_bitmap_next_set_bit()
116 (bit) = metal_bitmap_next_set_bit((bitmap), (bit), (max)))
124 bit < max && !metal_bitmap_is_bit_clear(bitmap, bit); in metal_bitmap_next_clear_bit()
125 bit ++) in metal_bitmap_next_clear_bit()
127 return bit; in metal_bitmap_next_clear_bit()
[all …]
/bsp/cvitek/drivers/
A Ddrv_gpio.c79 pol |= BIT(bit); in dwapb_toggle_trigger()
90 bit = PIN_NO(pin); in dwapb_pin_mode()
114 bit = PIN_NO(pin); in dwapb_pin_write()
119 reg_val = (value ? (reg_val | BIT(bit)) : (reg_val & (~BIT(bit)))); in dwapb_pin_write()
128 bit = PIN_NO(pin); in dwapb_pin_read()
178 bit = PIN_NO(pin); in dwapb_pin_attach_irq()
193 ip_val = (polarity ? (ip_val | BIT(bit)) : (ip_val & (~BIT(bit)))); in dwapb_pin_attach_irq()
209 ip_val = (rising ? (ip_val | BIT(bit)) : (ip_val & (~BIT(bit)))); in dwapb_pin_attach_irq()
243 bit = PIN_NO(pin); in dwapb_pin_irq_enable()
248 reg_val = (enabled ? (reg_val | BIT(bit)) : (reg_val & (~BIT(bit)))); in dwapb_pin_irq_enable()
[all …]
/bsp/smartfusion2/CMSIS/
A Dhw_reg_io.h70 static __INLINE void set_bit_reg32(volatile uint32_t * reg, uint8_t bit) in set_bit_reg32() argument
72 HW_REG_BIT(reg,bit) = 0x1; in set_bit_reg32()
76 HW_REG_BIT(reg,bit) = 0x1; in set_bit_reg16()
78 static __INLINE void set_bit_reg8(volatile uint8_t * reg, uint8_t bit) in set_bit_reg8() argument
80 HW_REG_BIT(reg,bit) = 0x1; in set_bit_reg8()
87 HW_REG_BIT(reg,bit) = 0x0; in clear_bit_reg32()
91 HW_REG_BIT(reg,bit) = 0x0; in clear_bit_reg16()
95 HW_REG_BIT(reg,bit) = 0x0; in clear_bit_reg8()
102 return (HW_REG_BIT(reg,bit)); in read_bit_reg32()
106 return (HW_REG_BIT(reg,bit)); in read_bit_reg16()
[all …]
/bsp/yichip/yc3122-pos/Libraries/sdk/
A Dyc_uart.c97 DMAx->CTRL.bit.LOOPBACK = 1; in UART_Init()
98 DMAx->CTRL.bit.RESET = 1; in UART_Init()
99 DMAx->CTRL.bit.RESET = 0; in UART_Init()
108 UARTx->CTRL.bit.RESET_BAUD = ENABLE; in UART_Init()
179 while (DMAx->STATUS.bit.DONE != 1); in UART_SendData()
202 DMAx->CTRL.bit.START = 1; in UART_SendBuf()
204 while (DMAx->STATUS.bit.DONE != 1); in UART_SendBuf()
219 return UARTx->RX_DATA.bit.VAL; in UART_ReceiveData()
261 UARTx->CTRL.bit.FLOW_CTRL = NewState; in UART_AutoFlowCtrlCmd()
280 else if(UARTx->BAUD.bit.TX_INT_EN) in UART_GetITIdentity()
[all …]
/bsp/efm32/Libraries/emlib/src/
A Dem_lcd.c279 if (bit < 32) in LCD_SegmentSet()
286 bit -= 32; in LCD_SegmentSet()
292 if (bit < 32) in LCD_SegmentSet()
299 bit -= 32; in LCD_SegmentSet()
305 if (bit < 32) in LCD_SegmentSet()
312 bit -= 32; in LCD_SegmentSet()
325 bit -= 32; in LCD_SegmentSet()
340 bit -= 32; in LCD_SegmentSet()
355 bit -= 32; in LCD_SegmentSet()
370 bit -= 32; in LCD_SegmentSet()
[all …]
/bsp/yichip/yc3122-pos/Libraries/CMSIS/Device/YICHIP/YC3122/Include/
A Dyc3122.h287 } bit; member
295 } bit; member
314 } bit; member
323 } bit; member
332 } bit; member
360 } bit; member
376 } bit; member
387 } bit; member
396 } bit; member
418 } bit; member
[all …]
/bsp/ti/c28x/libraries/tms320f28379d/headers/include/
A DF2837xD_adc.h67 struct ADCCTL1_BITS bit; member
81 struct ADCCTL2_BITS bit; member
94 struct ADCBURSTCTL_BITS bit; member
107 struct ADCINTFLG_BITS bit; member
133 struct ADCINTOVF_BITS bit; member
249 struct ADCSOCFLG1_BITS bit; member
273 struct ADCSOCFRC1_BITS bit; member
297 struct ADCSOCOVF1_BITS bit; member
593 struct ADCEVTCLR_BITS bit; member
617 struct ADCEVTSEL_BITS bit; member
[all …]
A DF2837xD_sdfm.h77 struct SDIFLG_BITS bit; member
115 struct SDCTL_BITS bit; member
131 struct SDMFILEN_BITS bit; member
172 struct SDDPARM1_BITS bit; member
182 struct SDCMPH1_BITS bit; member
192 struct SDCMPL1_BITS bit; member
216 struct SDDATA1_BITS bit; member
267 struct SDCMPH2_BITS bit; member
277 struct SDCMPL2_BITS bit; member
301 struct SDDATA2_BITS bit; member
[all …]
A DF2837xD_sysctrl.h119 struct DC0_BITS bit; member
138 struct DC1_BITS bit; member
150 struct DC2_BITS bit; member
175 struct DC3_BITS bit; member
193 struct DC4_BITS bit; member
207 struct DC5_BITS bit; member
225 struct DC6_BITS bit; member
243 struct DC7_BITS bit; member
257 struct DC8_BITS bit; member
273 struct DC9_BITS bit; member
[all …]

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