| /bsp/raspberry-pi/raspi2/cpu/ |
| A D | cp15_gcc.S | 13 mrc p15, #0, r0, c0, c0, #5
18 mcr p15, #0, r0, c12, c0, #0
24 mrc p15, #0, r0, c1, c0, #0
26 mcr p15, #0, r0, c1, c0, #0
31 mrc p15, #0, r0, c1, c0, #0
33 mcr p15, #0, r0, c1, c0, #0
45 mrc p15, #1, r0, c0, c0, #1 @ read clid register
56 mcr p15, #2, r10, c0, c0, #0
58 mrc p15, #1, r1, c0, c0, #0
91 mrc p15, #0, r0, c1, c0, #0
[all …]
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| A D | start_gcc.S | 134 mrc p15, 0, r0, c1, c0, 1 ;@ set SMP bit in ACTLR
136 mcr p15, 0, r0, c1, c0, 1
143 mrc p15, 0, r0, c1, c0, 1 ;@ clear SMP bit in ACTLR
145 mcr p15, 0, r0, c1, c0, 1
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| /bsp/nxp/imx/imx6sx/cortex-a9/cpu/ |
| A D | cp15_gcc.S | 13 mrc p15, #0, r0, c0, c0, #5
18 mcr p15, #0, r0, c12, c0, #0
24 mrc p15, #0, r0, c1, c0, #0
26 mcr p15, #0, r0, c1, c0, #0
31 mrc p15, #0, r0, c1, c0, #0
33 mcr p15, #0, r0, c1, c0, #0
45 mrc p15, #1, r0, c0, c0, #1 @ read clid register
56 mcr p15, #2, r10, c0, c0, #0
58 mrc p15, #1, r1, c0, c0, #0
91 mrc p15, #0, r0, c1, c0, #0
[all …]
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| A D | cortexA9_gcc.S | 62 mrc p15, 0, r0, c0, c0, 5
76 MCR p15, 0, r0, c1, c0, 2
80 MCR p10, 7, r3, c8, c0, 0
92 mrc p15, 0, r0, c1, c0, 0
94 mcr p15, 0, r0, c1, c0, 0
104 mrc p15, 0, r0, c1, c0, 0
109 mcr p15, 0, r0, c1, c0, 0
223 mrc p15, 0, r0, c1, c0, 1 @ Read ACTLR
225 mcr p15, 0, r0, c1, c0, 1 @ Write ACTLR
240 mrc p15, 0, r0, c1, c0, 1 @ Read ACTLR
[all …]
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| /bsp/raspberry-pi/raspi3-32/cpu/ |
| A D | cp15_gcc.S | 13 mrc p15, #0, r0, c0, c0, #5
19 mrc p15, #0, r1, c1, c0, #0
21 mcr p15, #0, r1, c1, c0, #0
23 mcr p15, #0, r0, c12, c0, #0
29 mrc p15, #0, r0, c1, c0, #0
31 mcr p15, #0, r0, c1, c0, #0
36 mrc p15, #0, r0, c1, c0, #0
38 mcr p15, #0, r0, c1, c0, #0
59 mrc p15, #1, r0, c0, c0, #1 @ read clid register
70 mcr p15, #2, r10, c0, c0, #0
[all …]
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| A D | start_gcc.S | 126 mrc p15, 0, r0, c0, c0, 5
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| /bsp/allwinner_tina/libcpu/ |
| A D | mmu.c | 42 mrc p15, 0, value, c1, c0, 0 in mmu_enable()
44 mcr p15, 0, value, c1, c0, 0 in mmu_enable()
54 mrc p15, 0, value, c1, c0, 0 in mmu_disable()
56 mcr p15, 0, value, c1, c0, 0 in mmu_disable()
66 mrc p15, 0, value, c1, c0, 0 in mmu_enable_icache()
68 mcr p15, 0, value, c1, c0, 0 in mmu_enable_icache()
78 mrc p15, 0, value, c1, c0, 0 in mmu_enable_dcache()
80 mcr p15, 0, value, c1, c0, 0 in mmu_enable_dcache()
90 mrc p15, 0, value, c1, c0, 0 in mmu_disable_icache()
92 mcr p15, 0, value, c1, c0, 0 in mmu_disable_icache()
[all …]
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| A D | cpuport.c | 59 mrc p15, 0, i, c1, c0, 0 in cp15_rd()
71 mrc p15, 0, value, c1, c0, 0 in cache_enable()
73 mcr p15, 0, value, c1, c0, 0 in cache_enable()
83 mrc p15, 0, value, c1, c0, 0 in cache_disable()
85 mcr p15, 0, value, c1, c0, 0 in cache_disable()
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| A D | start_gcc.S | 123 mrc p15, 0, r2, c1, c0, 0
191 mrc p15, 0, r0, c1, c0, 0
196 mcr p15, 0, r0, c1, c0, 0
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| /bsp/ft2004/drivers/ |
| A D | ft2004_cpu.S | 16 mrc p15, 0, r0, c0, c0, 5
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| /bsp/hpmicro/libraries/hpm_sdk/drivers/src/ |
| A D | hpm_cam_drv.c | 35 config->csc_config.yuv2rgb_coef.c0 = 0x100; in cam_get_default_config()
46 config->csc_config.yuv2rgb_coef.c0 = 0x12A; in cam_get_default_config()
57 config->csc_config.yuv2rgb_coef.c0 = 0; in cam_get_default_config()
137 | CAM_CSC_COEF0_C0_SET(config->csc_config.yuv2rgb_coef.c0) in cam_init()
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| A D | hpm_lcdc_drv.c | 80 layer->csc_config.yuv2rgb_coef.c0 = 0x100; in lcdc_get_default_layer_config()
91 layer->csc_config.yuv2rgb_coef.c0 = 0x12A; in lcdc_get_default_layer_config()
102 layer->csc_config.yuv2rgb_coef.c0 = 0; in lcdc_get_default_layer_config()
227 | LCDC_LAYER_CSC_COEF0_C0_SET(layer->csc_config.yuv2rgb_coef.c0) in lcdc_config_layer()
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| A D | hpm_pdma_drv.c | 122 yuv2rgb_coef->c0 = 0x100; in pdma_get_default_yuv2rgb_coef_config()
131 yuv2rgb_coef->c0 = 0x12A; in pdma_get_default_yuv2rgb_coef_config()
140 yuv2rgb_coef->c0 = 0; in pdma_get_default_yuv2rgb_coef_config()
176 config->rgb2yuv_config.c0 = 0x4D; in pdma_get_default_output_config()
191 config->rgb2yuv_config.c0 = 0x42; in pdma_get_default_output_config()
206 config->rgb2yuv_config.c0 = 0; in pdma_get_default_output_config()
358 ptr->YUV2RGB_COEF0 = PDMA_YUV2RGB_COEF0_C0_SET(yuv2rgb->c0) in pdma_config_planes()
401 | PDMA_RGB2YUV_COEF0_C0_SET(config->rgb2yuv_config.c0) in pdma_config_output()
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| /bsp/hpmicro/libraries/hpm_sdk/drivers/inc/ |
| A D | hpm_display_common.h | 114 uint16_t c0; member
138 uint16_t c0; member
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| /bsp/phytium/board/ |
| A D | phytium_cpu_id.S | 55 mrc p15, 0, r0, c0, c0, 5
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| /bsp/phytium/aarch32/boot/ |
| A D | aarch32_boot.S | 182 mcr p15, 0, r0, c1, c0, 0 /* reset control register */
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| /bsp/allwinner/libraries/sunxi-hal/hal/source/disp2/disp/de/lowlevel_v2x/ |
| A D | de_peak_type.h | 86 unsigned int c0:9; member
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| A D | de_lti_type.h | 58 unsigned int c0:8; member
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| A D | de_lti.c | 181 lti_dev[sel][chno]->coef0.bits.c0 = 127; in de_lti_set_para()
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