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/bsp/xuantie/libraries/xuantie_libraries/csi/csi2/include/core/
A Dcore_rv32.h994 uint32_t cache; in csi_icache_enable() local
998 cache = __get_MHCR(); in csi_icache_enable()
1000 __set_MHCR(cache); in csi_icache_enable()
1016 uint32_t cache; in csi_icache_disable() local
1019 cache = __get_MHCR(); in csi_icache_disable()
1021 __set_MHCR(cache); in csi_icache_disable()
1062 uint32_t cache; in csi_dcache_enable() local
1066 cache = __get_MHCR(); in csi_dcache_enable()
1068 __set_MHCR(cache); in csi_dcache_enable()
1085 uint32_t cache; in csi_dcache_disable() local
[all …]
A Dcore_rv64.h1278 uint32_t cache; in csi_icache_enable() local
1282 cache = __get_MHCR(); in csi_icache_enable()
1284 __set_MHCR(cache); in csi_icache_enable()
1300 uint32_t cache; in csi_icache_disable() local
1303 cache = __get_MHCR(); in csi_icache_disable()
1305 __set_MHCR(cache); in csi_icache_disable()
1346 uint32_t cache; in csi_dcache_enable() local
1350 cache = __get_MHCR(); in csi_dcache_enable()
1352 __set_MHCR(cache); in csi_dcache_enable()
1369 uint32_t cache; in csi_dcache_disable() local
[all …]
/bsp/ESP32_C3/
A Desp32c3.gpb7 mem 0x20000000 0x3fefffff ro cache
9 mem 0x40000000 0x400fffff ro cache
10 mem 0x40100000 0x4013ffff rw cache
11 mem 0x40140000 0x5fffffff ro cache
/bsp/essemi/es32vf2264/libraries/RV_CORE/Include/
A Dcore_rv32.h867 uint32_t cache; in csi_icache_enable() local
871 cache = __get_MHCR(); in csi_icache_enable()
873 __set_MHCR(cache); in csi_icache_enable()
887 uint32_t cache; in csi_icache_disable() local
890 cache = __get_MHCR(); in csi_icache_disable()
892 __set_MHCR(cache); in csi_icache_disable()
924 uint32_t cache; in csi_dcache_enable() local
928 cache = __get_MHCR(); in csi_dcache_enable()
930 __set_MHCR(cache); in csi_dcache_enable()
946 uint32_t cache; in csi_dcache_disable() local
[all …]
/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/arch/risc-v/t-head/Core/Include/
A Dcore_rv64.h807 uint32_t cache; in csi_icache_enable() local
811 cache = __get_MHCR(); in csi_icache_enable()
813 __set_MHCR(cache); in csi_icache_enable()
826 uint32_t cache; in csi_icache_disable() local
829 cache = __get_MHCR(); in csi_icache_disable()
831 __set_MHCR(cache); in csi_icache_disable()
861 uint32_t cache; in csi_dcache_enable() local
865 cache = __get_MHCR(); in csi_dcache_enable()
867 __set_MHCR(cache); in csi_dcache_enable()
882 uint32_t cache; in csi_dcache_disable() local
[all …]
A Dcore_rv32.h1066 uint32_t cache; in csi_icache_enable() local
1070 cache = __get_MHCR(); in csi_icache_enable()
1072 __set_MHCR(cache); in csi_icache_enable()
1085 uint32_t cache; in csi_icache_disable() local
1088 cache = __get_MHCR(); in csi_icache_disable()
1090 __set_MHCR(cache); in csi_icache_disable()
1120 uint32_t cache; in csi_dcache_enable() local
1124 cache = __get_MHCR(); in csi_dcache_enable()
1126 __set_MHCR(cache); in csi_dcache_enable()
1141 uint32_t cache; in csi_dcache_disable() local
[all …]
/bsp/thead-smart/drivers/
A Dcore_rv32.h968 uint32_t cache; in csi_icache_enable() local
972 cache = __get_MHCR(); in csi_icache_enable()
974 __set_MHCR(cache); in csi_icache_enable()
988 uint32_t cache; in csi_icache_disable() local
991 cache = __get_MHCR(); in csi_icache_disable()
993 __set_MHCR(cache); in csi_icache_disable()
1025 uint32_t cache; in csi_dcache_enable() local
1029 cache = __get_MHCR(); in csi_dcache_enable()
1031 __set_MHCR(cache); in csi_dcache_enable()
1047 uint32_t cache; in csi_dcache_disable() local
[all …]
/bsp/allwinner/libraries/sunxi-hal/hal/source/spinor/
A Dcache.c22 cache_t cache; member
122 if (nc->cache.buf) in nor_cache_init()
148 delete_cache(&nc->cache); in nor_cache_init()
158 delete_cache(&nc->cache); in nor_cache_exit()
185 cache_t *c = &nc->cache; in get_addr_by_page()
194 cache_t *c = &nc->cache; in get_addr_by_blk()
250 cache_t *c = &nc->cache; in nor_flush_write()
288 clear_cache(&nc->cache); in nor_flush_cache()
296 cache_t *c = &nc->cache; in nor_cache_write()
377 cache_t *c = &nc->cache; in nor_cache_read()
[all …]
A DKconfig28 enable cache since it does really improve performance. Erasing should be
38 4K block and nor cache to get more operations together.
43 bool "Enable spinor cache layer"
48 32K/64K erase operation. This cache layer holds a 64K buffer. It just
49 will cache sequential erase/write operation. There are three ways to
50 flush cache.
58 This cache layer with the littlefs turns out no loss of data, but the
63 cache. Also, you can flush cache for fatal data too. In a word,
A DMakefile13 obj-$(CONFIG_DRIVERS_SPINOR_CACHE) += cache.o
/bsp/microchip/samd51-adafruit-metro-m4/bsp/hal/src/
A Dhal_cache.c67 int32_t cache_configure(const void *hw, struct _cache_cfg *cache) in cache_configure() argument
69 return _cmcc_configure(hw, cache); in cache_configure()
/bsp/microchip/samd51-seeed-wio-terminal/bsp/hal/src/
A Dhal_cache.c67 int32_t cache_configure(const void *hw, struct _cache_cfg *cache) in cache_configure() argument
69 return _cmcc_configure(hw, cache); in cache_configure()
/bsp/microchip/same54/bsp/hal/src/
A Dhal_cache.c67 int32_t cache_configure(const void *hw, struct _cache_cfg *cache) in cache_configure() argument
69 return _cmcc_configure(hw, cache); in cache_configure()
/bsp/xuantie/xiaohui/c907/
A DREADME.md24 • 指令 cache，四路组相连结构， 64B 缓存行， 8KB-64KB 可配置， VIPT；
25 • 数据 cache，四路组相连结构， 64B 缓存行， 8KB-64KB 可配置， VIPT 模拟 PIPT；
/bsp/xuantie/xiaohui/c908/
A DREADME.md24 • 指令 cache，四路组相连结构， 64B 缓存行， 8KB-64KB 可配置， VIPT；
25 • 数据 cache，四路组相连结构， 64B 缓存行， 8KB-64KB 可配置， VIPT 模拟 PIPT；
/bsp/microchip/samd51-adafruit-metro-m4/bsp/hpl/usb/
A Dhpl_usb.c435 void *cache; member
507 uint8_t *cache; member
1047 _usbd_ep_set_buf(epn, 1, (uint32_t)ept->cache); in _usb_d_dev_in_next()
1131 _usbd_ep_set_buf(epn, 0, (uint32_t)ept->cache); in _usb_d_dev_out_next()
1151 _usbd_ep_set_buf(epn, 0, (uint32_t)ept->cache); in _usb_d_dev_out_next()
1179 _usbd_ep_set_buf(epn, 0, (uint32_t)ept->cache); in _usb_d_dev_out_next()
1613 _usbd_ep_set_buf(epn, 0, (uint32_t)ept->cache); in _usb_d_dev_trans_setup()
1647 if (pcfg->cache == NULL) { in _usb_d_dev_ep_init()
1656 ept->cache = (uint8_t *)(dir ? pcfg->i_cache : pcfg->cache); in _usb_d_dev_ep_init()
1937 if (!ept->cache) { in _usb_d_dev_ep_trans()
[all …]
/bsp/microchip/samd51-seeed-wio-terminal/bsp/hpl/usb/
A Dhpl_usb.c435 void *cache; member
507 uint8_t *cache; member
1047 _usbd_ep_set_buf(epn, 1, (uint32_t)ept->cache); in _usb_d_dev_in_next()
1131 _usbd_ep_set_buf(epn, 0, (uint32_t)ept->cache); in _usb_d_dev_out_next()
1151 _usbd_ep_set_buf(epn, 0, (uint32_t)ept->cache); in _usb_d_dev_out_next()
1179 _usbd_ep_set_buf(epn, 0, (uint32_t)ept->cache); in _usb_d_dev_out_next()
1613 _usbd_ep_set_buf(epn, 0, (uint32_t)ept->cache); in _usb_d_dev_trans_setup()
1647 if (pcfg->cache == NULL) { in _usb_d_dev_ep_init()
1656 ept->cache = (uint8_t *)(dir ? pcfg->i_cache : pcfg->cache); in _usb_d_dev_ep_init()
1937 if (!ept->cache) { in _usb_d_dev_ep_trans()
[all …]
/bsp/ft2004/libraries/doc/
A DChangeLog.md60 1. Added descriptor cache handling
66 1. Added cache to drv_sdctrl
/bsp/xuantie/smartl/e906/
A DREADME.md22 • 可选配指令 cache，两路组相连结构， 2KiB-32KiB 可配置；
23 • 可选配数据 cache，两路组相连结构， 2KiB-32KiB 可配置；
/bsp/stm32/stm32h723-st-nucleo/
A DREADME.md7 …ypes. The Cortex -M7 core includes 32 Kbytes of instruction cache and 32 Kbytes of data cache. STM…
17 …- 32-bit Arm® Cortex®-M7 CPU with DP-FPU, L1 cache: 32-Kbyte data cache and 32-Kbyte instruction c…
/bsp/ESP32_C3/idf_port/ld/
A Dmemory.ld38 …* All these values assume the flash cache is on, and have the blocks this uses subtracted from th…
48 * Flash cache has 64KB pages. The .bin file which is flashed to the chip
50 * header. Setting this offset makes it simple to meet the flash cache MMU's
/bsp/microchip/samd51-adafruit-metro-m4/bsp/hal/include/
A Dhal_cache.h81 int32_t cache_configure(const void *hw, struct _cache_cfg *cache);
/bsp/microchip/samd51-seeed-wio-terminal/bsp/hal/include/
A Dhal_cache.h81 int32_t cache_configure(const void *hw, struct _cache_cfg *cache);
/bsp/microchip/same54/bsp/hal/include/
A Dhal_cache.h81 int32_t cache_configure(const void *hw, struct _cache_cfg *cache);
/bsp/microchip/samd51-adafruit-metro-m4/bsp/hal/documentation/
A Dusb_device_async.rst178 cache to buffer input/output data, to remove upper limits. The configuration
181 * For control endpoints, cache buffer must be enabled to fill setup packet.
184 * For OUT endpoints, if the cache is allocated, it's possible to pass unaligned
188 * For IN endpoints, if the cache is allocated, it's possible to pass buffer

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