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Searched refs:ccr (Results 1 – 6 of 6) sorted by relevance

/bsp/rockchip/common/rk_hal/lib/hal/src/
A Dhal_pl330.c176 #define BRST_LEN(ccr) ((((ccr) >> CC_SRCBRSTLEN_SHFT) & 0xf) + 1) argument
179 #define BYTE_TO_BURST(b, ccr) ((b) / BRST_SIZE(ccr) / BRST_LEN(ccr)) argument
180 #define BURST_TO_BYTE(c, ccr) ((c) * BRST_SIZE(ccr) * BRST_LEN(ccr)) argument
181 #define BYTE_MOD_BURST_LEN(b, ccr) (((b) / BRST_SIZE(ccr)) % BRST_LEN(ccr)) argument
825 unsigned int ccr = pxs->ccr; in _Period() local
897 uint32_t ccr = pxs->ccr; in _Setup_Loops() local
939 unsigned int ccr = pxs->ccr; in _Setup_Xfer() local
959 uint32_t ccr = pxs->ccr; in _Setup_Xfer_Cyclic() local
964 bursts = x->length / (BRST_SIZE(ccr) * BRST_LEN(ccr) in _Setup_Xfer_Cyclic()
967 bursts = x->length / (BRST_SIZE(ccr) * BRST_LEN(ccr) in _Setup_Xfer_Cyclic()
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/bsp/mm32/libraries/MM32F3270_HAL/MM32F3270_HAL_Driver/Src/
A Dhal_dma.c13 uint32_t ccr = 0u; in DMA_InitChannel() local
18 ccr |= DMA_CCR_DIR_MASK; in DMA_InitChannel()
24 ccr |= DMA_CCR_MEM2MEM_MASK; in DMA_InitChannel()
29 ccr |= DMA_CCR_ARE_MASK; in DMA_InitChannel()
33 ccr |= (DMA_CCR_ARE_MASK | DMA_CCR_CIRC_MASK); in DMA_InitChannel()
36 ccr |= DMA_CCR_PINC(init->PeriphAddrIncMode) in DMA_InitChannel()
43 DMAx->CH[channel].CCR = ccr; in DMA_InitChannel()
A Dhal_uart.c12 uint32_t ccr = UARTx->CCR & ~( UART_CCR_PEN_MASK in UART_Init() local
19 ccr |= UART_CCR_CHAR(init->WordLength); in UART_Init()
24 ccr |= UART_CCR_SPB0_MASK; in UART_Init()
28 ccr |= UART_CCR_SPB1_MASK; in UART_Init()
34 ccr |= UART_CCR_PEN_MASK; in UART_Init()
38 ccr |= UART_CCR_PEN_MASK | UART_CCR_PSEL_MASK; in UART_Init()
40 UARTx->CCR = ccr; in UART_Init()
/bsp/rv32m1_vega/rv32m1_sdk_riscv/devices/RV32M1/drivers/
A Dfsl_mu.c150 uint32_t ccr = base->CCR & ~(MU_CCR_HR_MASK | MU_CCR_RSTH_MASK | MU_CCR_BOOT_MASK); in MU_HardwareResetOtherCore() local
152 ccr |= MU_CCR_BOOT(bootMode); in MU_HardwareResetOtherCore()
156 ccr |= MU_CCR_RSTH_MASK; in MU_HardwareResetOtherCore()
164 base->CCR = ccr | MU_CCR_HR_MASK; in MU_HardwareResetOtherCore()
180 base->CCR = ccr; in MU_HardwareResetOtherCore()
/bsp/rockchip/common/rk_hal/lib/hal/inc/
A Dhal_pl330.h163 uint32_t ccr; member
/bsp/xuantie/libraries/xuantie_libraries/csi/csi2/include/core/
A Dcsi_gcc.h278 __ALWAYS_STATIC_INLINE void __set_CCR(uint32_t ccr) in __set_CCR() argument
281 __ASM volatile("mtcr %0, cr18\n" : : "r"(ccr)); in __set_CCR()
283 __ASM volatile("mtcr %0, cr<18, 0>\n" : : "r"(ccr)); in __set_CCR()

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