1 /* 2 * Allwinner SoCs display driver. 3 * 4 * Copyright (C) 2016 Allwinner. 5 * 6 * This file is licensed under the terms of the GNU General Public 7 * License version 2. This program is licensed "as is" without any 8 * warranty of any kind, whether express or implied. 9 */ 10 11 /******************************************************************************* 12 * All Winner Tech, All Right Reserved. 2014-2015 Copyright (c) 13 * 14 * File name : de_peak_type.h 15 * 16 * Description : display engine 2.0 peak struct declaration 17 * 18 * History : 2014/03/26 vito cheng v0.1 Initial version 19 * 20 ******************************************************************************/ 21 22 #ifndef __DE_PEAK_TYPE_H__ 23 #define __DE_PEAK_TYPE_H__ 24 25 #include "de_rtmx.h" 26 27 #define PEAK_PARA_NUM 3 28 #define PEAK_MODE_NUM 3 29 30 union LP_CTRL_REG { 31 unsigned int dwval; 32 struct { 33 unsigned int en:1; 34 unsigned int res0:7; 35 unsigned int win_en:1; 36 unsigned int res1:23; 37 } bits; 38 }; 39 40 union LP_SIZE_REG { 41 unsigned int dwval; 42 struct { 43 unsigned int width:12; 44 unsigned int res0:4; 45 unsigned int height:12; 46 unsigned int res1:4; 47 } bits; 48 }; 49 50 union LP_WIN0_REG { 51 unsigned int dwval; 52 struct { 53 unsigned int win_left:12; 54 unsigned int res0:4; 55 unsigned int win_top:12; 56 unsigned int res1:4; 57 } bits; 58 }; 59 60 union LP_WIN1_REG { 61 unsigned int dwval; 62 struct { 63 unsigned int win_right:12; 64 unsigned int res0:4; 65 unsigned int win_bot:12; 66 unsigned int res1:4; 67 } bits; 68 }; 69 70 union LP_FILTER_REG { 71 unsigned int dwval; 72 struct { 73 unsigned int bp1_ratio:6; 74 unsigned int res0:2; 75 unsigned int bp0_ratio:6; 76 unsigned int res1:2; 77 unsigned int hp_ratio:6; 78 unsigned int res2:9; 79 unsigned int filter_sel:1; 80 } bits; 81 }; 82 83 union LP_CSTM_FILTER0_REG { 84 unsigned int dwval; 85 struct { 86 unsigned int c0:9; 87 unsigned int res0:7; 88 unsigned int c1:9; 89 unsigned int res1:7; 90 } bits; 91 }; 92 93 union LP_CSTM_FILTER1_REG { 94 unsigned int dwval; 95 struct { 96 unsigned int c2:9; 97 unsigned int res0:7; 98 unsigned int c3:9; 99 unsigned int res1:7; 100 } bits; 101 }; 102 103 union LP_CSTM_FILTER2_REG { 104 unsigned int dwval; 105 struct { 106 unsigned int c4:9; 107 unsigned int res0:23; 108 } bits; 109 }; 110 111 union LP_GAIN_REG { 112 unsigned int dwval; 113 struct { 114 unsigned int gain:8; 115 unsigned int res0:24; 116 } bits; 117 }; 118 119 union LP_GAINCTRL_REG { 120 unsigned int dwval; 121 struct { 122 unsigned int beta:5; 123 unsigned int res0:11; 124 unsigned int dif_up:8; 125 unsigned int res1:8; 126 } bits; 127 }; 128 129 union LP_SHOOTCTRL_REG { 130 unsigned int dwval; 131 struct { 132 unsigned int neg_gain:6; 133 unsigned int res0:26; 134 } bits; 135 }; 136 137 union LP_CORING_REG { 138 unsigned int dwval; 139 struct { 140 unsigned int corthr:8; 141 unsigned int res0:24; 142 } bits; 143 }; 144 145 struct __peak_reg_t { 146 union LP_CTRL_REG ctrl; /* 0x0000 */ 147 union LP_SIZE_REG size; /* 0x0004 */ 148 union LP_WIN0_REG win0; /* 0x0008 */ 149 union LP_WIN1_REG win1; /* 0x000c */ 150 union LP_FILTER_REG filter; /* 0x0010 */ 151 union LP_CSTM_FILTER0_REG cfilter0; /* 0x0014 */ 152 union LP_CSTM_FILTER1_REG cfilter1; /* 0x0018 */ 153 union LP_CSTM_FILTER2_REG cfilter2; /* 0x001c */ 154 union LP_GAIN_REG gain; /* 0x0020 */ 155 union LP_GAINCTRL_REG gainctrl; /* 0x0024 */ 156 union LP_SHOOTCTRL_REG shootctrl; /* 0x0028 */ 157 union LP_CORING_REG coring; /* 0x002c */ 158 }; 159 160 struct __peak_config_data { 161 /* peak */ 162 unsigned int peak_en; 163 unsigned int gain; 164 unsigned int hp_ratio; 165 unsigned int bp0_ratio; 166 167 /* window */ 168 unsigned int win_en; 169 struct de_rect win; 170 171 }; 172 173 #endif 174