Home
last modified time | relevance | path

Searched refs:ch (Results 1 – 25 of 728) sorted by relevance

12345678910>>...30

/bsp/k230/drivers/interdrv/pdma/
A Ddrv_pdma.c64 (((ch) >= 0 && (ch) < PDMA_CH_MAX) ? \
207 if (ch == RT_NULL) in k230_pdma_request_channel()
247 *ch = i; in k230_pdma_request_channel()
263 *ch = PDMA_CH_MAX; in k230_pdma_request_channel()
283 if (!PDMA_CH_MENUCONFIG_ENABLED(ch) || !PDMA_CH_IS_ENABLED(ch)) in k230_pdma_release_channel()
334 if (!PDMA_CH_MENUCONFIG_ENABLED(ch) || !PDMA_CH_IS_ENABLED(ch)) in k230_pdma_start()
358 PDMA_CH_START(ch); in k230_pdma_start()
381 if (!PDMA_CH_MENUCONFIG_ENABLED(ch) || !PDMA_CH_IS_ENABLED(ch)) in k230_pdma_stop()
521 if (!PDMA_CH_MENUCONFIG_ENABLED(ch) || !PDMA_CH_IS_ENABLED(ch)) in k230_pdma_config()
585 PDMA_CH_STOP(ch); in _k230_pdma_safe_stop()
[all …]
/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/drivers/
A Dcodec.c162 ch->callback = NULL; in csi_codec_output_open()
229 ch->arg = arg; in csi_codec_output_attach_callback()
242 ch->arg = NULL; in csi_codec_output_detach_callback()
270 ch->dma = dma; in csi_codec_output_link_dma()
385 memset(ch->ring_buf->buffer, 0, ch->ring_buf->size); in csi_codec_output_buffer_reset()
388 if ((ch->ring_buf->read == 0U) && (ch->ring_buf->write == 0U)) { in csi_codec_output_buffer_reset()
559 ch->arg = arg; in csi_codec_input_attach_callback()
572 ch->arg = NULL; in csi_codec_input_detach_callback()
600 ch->dma = dma; in csi_codec_input_link_dma()
690 memset(ch->ring_buf->buffer, 0, ch->ring_buf->size); in csi_codec_input_buffer_reset()
[all …]
/bsp/maxim/libraries/MAX32660PeriphDriver/Source/
A Ddma.c182 if (CHECK_HANDLE(ch)) { in DMA_ReleaseChannel()
188 dma_resource[ch].regs->st = dma_resource[ch].regs->st; in DMA_ReleaseChannel()
235 if (CHECK_HANDLE(ch)) { in DMA_SetSrcDstCnt()
247 int DMA_SetReload(int ch, in DMA_SetReload() argument
316 int DMA_ClearFlags(int ch) in DMA_ClearFlags() argument
319 dma_resource[ch].regs->st = dma_resource[ch].regs->st; in DMA_ClearFlags()
328 int DMA_Start(int ch) in DMA_Start() argument
345 int DMA_Stop(int ch) in DMA_Stop() argument
367 void DMA_Handler(int ch) in DMA_Handler() argument
371 dma_resource[ch].cb(ch, E_NO_ERROR); in DMA_Handler()
[all …]
/bsp/allwinner/libraries/sunxi-hal/hal/source/msgbox/msgbox_sx/
A Dhal_msgbox_sx.c86 ch->cb_rx(data, ch->data); in msgbox_rev_handler()
103 if (ch->idx >= ch->len) { in msgbox_send_handler()
108 if (ch->idx < ch->len) in msgbox_send_handler()
109 data |= ch->send[ch->idx++] << (i << 3); in msgbox_send_handler()
121 ch->cb_tx_done(ch->idx, ch->data); in msgbox_send_handler()
144 ch->mb = mb; in msgbox_alloc_channel_sx()
147 ch->dir = dir; in msgbox_alloc_channel_sx()
163 return ch; in msgbox_alloc_channel_sx()
184 ch->send = d; in msgbox_channel_send_data_sx()
185 ch->len = len; in msgbox_channel_send_data_sx()
[all …]
/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/src/
A Dtae32f53xx_ll_dma.c162 if (ch == DMA_CHANNEL_0) { in LL_DMA_Init()
164 } else if (ch == DMA_CHANNEL_1) { in LL_DMA_Init()
270 …if (ch < DMA_CHANNEL_NUM && !READ_BIT(dma_pri_ctrl.ch_used, BIT(ch)) && (dma_pri_ctrl.ch_ctrl[ch].… in LL_DMA_ChReqSpecific()
273 ch = DMA_CHANNEL_INVALID; in LL_DMA_ChReqSpecific()
276 return ch; in LL_DMA_ChReqSpecific()
315 if (ch >= DMA_CHANNEL_NUM) { in LL_DMA_Start_CPU()
364 if (ch == DMA_CHANNEL_0) { in LL_DMA_Start_CPU()
389 if (ch == DMA_CHANNEL_0) { in LL_DMA_Start_IT()
417 if (ch == DMA_CHANNEL_0) { in LL_DMA_Stop_CPU()
446 if (ch == DMA_CHANNEL_0) { in LL_DMA_Stop_IT()
[all …]
/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/
A Dhpm_acmp_drv.h139 ptr->CHANNEL[ch].DMAEN = (ptr->CHANNEL[ch].DMAEN & ~mask) in acmp_channel_dma_request_enable()
158 ptr->CHANNEL[ch].IRQEN = (ptr->CHANNEL[ch].IRQEN & ~mask) in acmp_channel_enable_irq()
173 ptr->CHANNEL[ch].CFG = (ptr->CHANNEL[ch].CFG & ~ACMP_CHANNEL_CFG_DACEN_MASK) in acmp_channel_enable_dac()
188 ptr->CHANNEL[ch].CFG = (ptr->CHANNEL[ch].CFG & ~ACMP_CHANNEL_CFG_HPMODE_MASK) in acmp_channel_enable_hpmode()
201 ptr->CHANNEL[ch].CFG = (ptr->CHANNEL[ch].CFG & ~ACMP_CHANNEL_CFG_HYST_MASK) in acmp_channel_set_hyst()
216 ptr->CHANNEL[ch].CFG = (ptr->CHANNEL[ch].CFG & ~ACMP_CHANNEL_CFG_CMPEN_MASK) in acmp_channel_enable_cmp()
231 ptr->CHANNEL[ch].CFG = (ptr->CHANNEL[ch].CFG & ~ACMP_CHANNEL_CFG_CMPOEN_MASK) in acmp_channel_enable_cmp_output()
261 ptr->CHANNEL[ch].CFG = (ptr->CHANNEL[ch].CFG & ~ACMP_CHANNEL_CFG_WINEN_MASK) in acmp_channel_enable_cmp_window_mode()
276 ptr->CHANNEL[ch].CFG = (ptr->CHANNEL[ch].CFG & ~ACMP_CHANNEL_CFG_OPOL_MASK) in acmp_channel_invert_output()
304 ptr->CHANNEL[ch].CFG = (ptr->CHANNEL[ch].CFG & ~ACMP_CHANNEL_CFG_SYNCEN_MASK) in acmp_channel_enable_sync()
[all …]
A Dhpm_sdm_drv.h23 #define CHN_SAMPLING_MODE_SHIFT(ch) ((ch) * 3U + SDM_CTRL_CHMD_SHIFT) argument
24 #define CHN_SAMPLING_MODE_MASK(ch) (SAMPLING_MODE_MASK << CHN_SAMPLING_MODE_SHIFT(ch)) argument
27 #define CHN_EN_MASK(ch) (CH0_EN_MASK << (ch)) argument
29 #define CHN_ERR_MASK(ch) (SDM_INT_EN_CH0ERR_MASK << (ch)) argument
30 #define CHN_DRY_MASK(ch) (SDM_INT_EN_CH0DRY_MASK << (ch)) argument
226 return (((ptr->STATUS) & CHN_DRY_MASK(ch)) == CHN_DRY_MASK(ch)); in sdm_get_channel_data_ready_status()
239 return (((ptr->STATUS) & CHN_ERR_MASK(ch)) == CHN_ERR_MASK(ch)); in sdm_get_channel_data_error_status()
275 return ptr->CH[ch].SDST; in sdm_get_channel_filter_status()
299 return ptr->CH[ch].SDFIFO; in sdm_get_channel_fifo_data()
335 ptr->CH[ch].SCHTL = value; in sdm_set_channel_comparator_high_threshold()
[all …]
A Dhpm_tamp_drv.h106 ch >>= 1u; in tamp_set_ch_enable()
108 ptr->TAMP[ch].CONTROL |= TAMP_TAMP_CONTROL_ENABLE_MASK; in tamp_set_ch_enable()
110 ptr->TAMP[ch].CONTROL &= ~TAMP_TAMP_CONTROL_ENABLE_MASK; in tamp_set_ch_enable()
124 ch >>= 1u; in tamp_set_ch_config_lock()
126 ptr->TAMP[ch].CONTROL |= TAMP_TAMP_CONTROL_LOCK_MASK; in tamp_set_ch_config_lock()
128 ptr->TAMP[ch].CONTROL &= ~TAMP_TAMP_CONTROL_LOCK_MASK; in tamp_set_ch_config_lock()
164 static inline bool tamp_check_ch_flag(TAMP_Type *ptr, uint8_t ch) in tamp_check_ch_flag() argument
176 static inline void tamp_clear_ch_flag(TAMP_Type *ptr, uint8_t ch) in tamp_clear_ch_flag() argument
178 ptr->TAMP_FLAG = TAMP_TAMP_FLAG_FLAG_SET(1u << ch); in tamp_clear_ch_flag()
192 ptr->IRQ_EN |= TAMP_IRQ_EN_IRQ_EN_SET(1u << ch); in tamp_enable_ch_irq()
[all …]
/bsp/xuantie/libraries/xuantie_libraries/csi/csi2/include/drv/
A Dcodec.h160 void csi_codec_output_detach_callback(csi_codec_output_t *ch);
167 void csi_codec_output_close(csi_codec_output_t *ch);
203 csi_error_t csi_codec_output_start(csi_codec_output_t *ch);
210 void csi_codec_output_stop(csi_codec_output_t *ch);
217 csi_error_t csi_codec_output_pause(csi_codec_output_t *ch);
224 csi_error_t csi_codec_output_resume(csi_codec_output_t *ch);
318 void csi_codec_input_detach_callback(csi_codec_input_t *ch);
325 void csi_codec_input_close(csi_codec_input_t *ch);
361 csi_error_t csi_codec_input_start(csi_codec_input_t *ch);
368 void csi_codec_input_stop(csi_codec_input_t *ch);
[all …]
/bsp/hpmicro/libraries/hpm_sdk/drivers/src/
A Dhpm_dmav2_drv.c13 ch->en_infiniteloop = false; in dma_default_channel_config()
23 ch->linked_ptr = 0; in dma_default_channel_config()
30 ch->swap_table = 0; in dma_default_channel_config()
41 || (ch->en_infiniteloop && (ch->linked_ptr != 0)) in dma_setup_channel()
46 if ((ch->size_in_byte & ((1 << ch->dst_width) - 1)) in dma_setup_channel()
47 || (ch->src_addr & ((1 << ch->src_width) - 1)) in dma_setup_channel()
48 || (ch->dst_addr & ((1 << ch->dst_width) - 1)) in dma_setup_channel()
49 || ((1 << ch->src_width) & ((1 << ch->dst_width) - 1)) in dma_setup_channel()
50 || ((ch->linked_ptr & 0x7))) { in dma_setup_channel()
56 …ptr->CHCTRL[ch_num].TRANSIZE = DMAV2_CHCTRL_TRANSIZE_TRANSIZE_SET(ch->size_in_byte >> ch->src_widt… in dma_setup_channel()
[all …]
A Dhpm_dma_drv.c17 …|| ((ch->dst_mode == DMA_HANDSHAKE_MODE_HANDSHAKE) && (ch->src_mode == DMA_HANDSHAKE_MODE_HANDSHAK… in dma_setup_channel()
20 if ((ch->size_in_byte & ((1 << ch->dst_width) - 1)) in dma_setup_channel()
21 || (ch->src_addr & ((1 << ch->src_width) - 1)) in dma_setup_channel()
22 || (ch->dst_addr & ((1 << ch->dst_width) - 1)) in dma_setup_channel()
23 || ((1 << ch->src_width) & ((1 << ch->dst_width) - 1)) in dma_setup_channel()
24 || ((ch->linked_ptr & 0x7))) { in dma_setup_channel()
29 …ptr->CHCTRL[ch_num].TRANSIZE = DMA_CHCTRL_TRANSIZE_TRANSIZE_SET(ch->size_in_byte >> ch->src_width); in dma_setup_channel()
51 | ch->interrupt_mask; in dma_setup_channel()
65 ch->priority = DMA_CHANNEL_PRIORITY_LOW; in dma_default_channel_config()
72 ch->linked_ptr = 0; in dma_default_channel_config()
[all …]
A Dhpm_smix_drv.c118 ptr->DMAC_ERR_ST = 1 << ch; in smix_config_dma_channel()
119 ptr->DMAC_ABRT_ST = 1 << ch; in smix_config_dma_channel()
120 ptr->DMAC_TC_ST = 1 << ch; in smix_config_dma_channel()
139 ptr->DMA_CH[ch].CTL = tmp; in smix_config_dma_channel()
147 ptr->SOURCE_CH[ch].CTRL |= SMIX_SOURCE_CH_CTRL_FIFO_RESET_MASK; in smix_mixer_config_source_ch()
177 ptr->DST_CH[ch].CTRL |= SMIX_DST_CH_CTRL_SOFTRST_MASK; in smix_mixer_config_dst_ch()
178 ptr->DST_CH[ch].CTRL &= ~SMIX_DST_CH_CTRL_SOFTRST_MASK; in smix_mixer_config_dst_ch()
180 ptr->DST_CH[ch].GAIN = SMIX_DST_CH_GAIN_VAL_SET(dst->gain); in smix_mixer_config_dst_ch()
192 ptr->DST_CH[ch].SOURCE_EN = dst->src_ch_mask; in smix_mixer_config_dst_ch()
193 ptr->DST_CH[ch].SOURCE_ACT = dst->src_ch_mask; in smix_mixer_config_dst_ch()
[all …]
/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/
A Dbflb_pwm_v1.c13 regval = getreg32(reg_base + PWM0_CONFIG_OFFSET + ch * 0x20); in bflb_pwm_v1_channel_init()
15 putreg32(regval, reg_base + PWM0_CONFIG_OFFSET + ch * 0x20); in bflb_pwm_v1_channel_init()
27 regval = getreg32(reg_base + PWM0_CONFIG_OFFSET + ch * 0x20); in bflb_pwm_v1_channel_init()
37 putreg32(regval, reg_base + PWM0_CONFIG_OFFSET + ch * 0x20); in bflb_pwm_v1_channel_init()
42 putreg32(regval, reg_base + PWM0_CLKDIV_OFFSET + ch * 0x20); in bflb_pwm_v1_channel_init()
73 putreg32(0, reg_base + PWM0_CLKDIV_OFFSET + ch * 0x20); in bflb_pwm_v1_channel_deinit()
76 putreg32(0, reg_base + PWM0_THRE1_OFFSET + ch * 0x20); in bflb_pwm_v1_channel_deinit()
79 putreg32(0, reg_base + PWM0_THRE2_OFFSET + ch * 0x20); in bflb_pwm_v1_channel_deinit()
82 putreg32(0, reg_base + PWM0_PERIOD_OFFSET + ch * 0x20); in bflb_pwm_v1_channel_deinit()
95 void bflb_pwm_v1_start(struct bflb_device_s *dev, uint8_t ch) in bflb_pwm_v1_start() argument
[all …]
/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/inc/
A Dtae32f53xx_ll_dma.h246 #define __LL_DMA_SrcAddr_Set(__DMA__, ch, addr) WRITE_REG((__DMA__)->CH[(ch)].SAR, addr) argument
256 #define __LL_DMA_DstAddr_Set(__DMA__, ch, addr) WRITE_REG((__DMA__)->CH[(ch)].DAR, addr) argument
373 #define __LL_DMA_ChannelRegCR0_Write(__DMA__, ch, val) WRITE_REG((__DMA__)->CH[(ch)].CR0, val) argument
410 #define __LL_DAM_ChannelRegCR1_Write(__DMA__, ch, val) WRITE_REG((__DMA__)->CH[(ch)].CR1, val) argument
429 #define __LL_DMA_SrcHandshakeMode_Set(__DMA__, ch) SET_BIT((__DMA__)->CH[(ch)].CR2, DMA_CH_CR2… argument
445 #define __LL_DMA_DstHandshakeMode_Set(__DMA__, ch) SET_BIT((__DMA__)->CH[(ch)].CR2, DMA_CH_CR2… argument
471 #define __LL_DMA_ChannelSuspend_Set(__DMA__, ch) SET_BIT((__DMA__)->CH[(ch)].CR2, DMA_CH_CR2… argument
487 #define __LL_DMA_ChannelPriHigh_Set(__DMA__, ch) SET_BIT((__DMA__)->CH[(ch)].CR2, DMA_CH_CR2… argument
504 #define __LL_DAM_ChannelRegCR2_Write(__DMA__, ch, val) WRITE_REG((__DMA__)->CH[(ch)].CR2, val) argument
531 #define __LL_DMA_FIFOModeHalf_Set(__DMA__, ch) SET_BIT((__DMA__)->CH[(ch)].CR3, DMA_CH_CR3… argument
[all …]
/bsp/k230/drivers/utest/
A Dtest_pdma.c57 rt_uint8_t ch; in test_pdma_request() local
68 err = k230_pdma_request_channel(&ch); in test_pdma_request()
75 err = k230_pdma_request_channel(&ch); in test_pdma_request()
89 rt_uint8_t ch; in test_pdma_tx() local
142 err = k230_pdma_start(ch); in test_pdma_tx()
154 err = k230_pdma_stop(ch); in test_pdma_tx()
157 err = k230_pdma_release_channel(ch); in test_pdma_tx()
167 rt_uint8_t ch; in test_pdma_rx() local
223 k230_pdma_start(ch); in test_pdma_rx()
236 err = k230_pdma_stop(ch); in test_pdma_rx()
[all …]
/bsp/cvitek/drivers/libraries/cv180x/pwm/
A Dcvi_pwm.h184 PWM_HLPERIODX(reg_base, ch) = value; in cvi_pwm_set_high_period_ch()
189 return PWM_HLPERIODX(reg_base, ch); in cvi_pwm_get_high_period_ch()
194 PWM_PERIODX(reg_base, ch) = value; in cvi_pwm_set_period_ch()
199 return PWM_PERIODX(reg_base, ch); in cvi_pwm_get_period_ch()
219 PWM_PWMSTART(reg_base) |= CVI_PWM_START_CH_EN(ch); in cvi_pwm_start_en_ch()
229 PWM_PWM_OE(reg_base) |= CVI_PWM_OUTPUT_CH_EN(ch); in cvi_pwm_output_en_ch()
239 CAP_FREQNUM(reg_base, ch) = value; in cvi_cap_set_freqnum_ch()
244 CAP_FREQEN(reg_base) |= CVI_CAP_FREQEN(ch); in cvi_cap_freq_en_ch()
249 CAP_FREQEN(reg_base) &= ~CVI_CAP_FREQEN(ch); in cvi_cap_freq_dis_ch()
254 return CAP_FREQDONE_NUM(reg_base, ch); in cvi_cap_get_freq_done_num_ch()
[all …]
/bsp/maxim/libraries/MAX32660PeriphDriver/Include/
A Ddma.h151 int DMA_ReleaseChannel(int ch);
174 int DMA_ConfigChannel(int ch,
198 int DMA_SetSrcDstCnt(int ch,
215 int DMA_SetReload(int ch,
250 int DMA_EnableInterrupt(int ch);
258 int DMA_DisableInterrupt(int ch);
275 int DMA_ClearFlags(int ch);
284 int DMA_Start(int ch);
292 int DMA_Stop(int ch);
301 mxc_dma_ch_regs_t *DMA_GetCHRegs(int ch);
[all …]
/bsp/fujitsu/mb9x/mb9bf618s/CMSIS/DeviceSupport/fujitsu/mb9bf61x/startup/arm/
A Dstartup_mb9bf61x.S92 DCD INT0_7_Handler ; 4: External Interrupt Request ch.0 to ch.7
93 DCD INT8_31_Handler ; 5: External Interrupt Request ch.8 to ch.31
119 DCD BT0_7_IRQHandler ; 31: Base Timer ch.0 to ch.7
126 DCD DMAC0_Handler ; 38: DMAC ch.0
127 DCD DMAC1_Handler ; 39: DMAC ch.1
128 DCD DMAC2_Handler ; 40: DMAC ch.2
129 DCD DMAC3_Handler ; 41: DMAC ch.3
130 DCD DMAC4_Handler ; 42: DMAC ch.4
131 DCD DMAC5_Handler ; 43: DMAC ch.5
132 DCD DMAC6_Handler ; 44: DMAC ch.6
[all …]
/bsp/ck802/libraries/common/dmac/
A Dck_dmac.c323 ch_opened[ch] = 1; in csi_dma_alloc_channel()
324 ch_num = ch; in csi_dma_alloc_channel()
344 if (handle == NULL || ch >= dma_priv->ch_num || ch < 0) { in csi_dma_release_channel()
349 status[ch] = DMA_STATE_FREE; in csi_dma_release_channel()
350 ch_opened[ch] = 0; in csi_dma_release_channel()
381 if (ch < 0) { in csi_dma_config()
459 if (handle == NULL || ch >= dma_priv->ch_num || ch < 0) { in csi_dma_start()
463 status[ch] = DMA_STATE_BUSY; in csi_dma_start()
485 if (ch >= dma_priv->ch_num || ch < 0) { in csi_dma_stop()
511 if (ch >= dma_priv->ch_num || ch < 0) { in csi_dma_get_status()
[all …]
/bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Include/
A Dald_timer.h202 ald_timer_active_channel_t ch; /**< Active channel */ member
465 ald_timer_channel_config_t ch[3]; /**< Configure of channel */ member
639 #define ALD_TIMER_CCx_ENABLE(handle, ch) (((ch) == ALD_TIMER_CHANNEL_4) ? \ argument
651 #define ALD_TIMER_CCx_DISABLE(handle, ch) (((ch) == ALD_TIMER_CHANNEL_4) ? \ argument
662 #define ALD_TIMER_CCxN_ENABLE(handle, ch) ((handle)->perh->CCEP |= (1 << (((ch) << 2) + 2))) argument
672 #define ALD_TIMER_CCxN_DISABLE(handle, ch) ((handle)->perh->CCEP &= ~(1 << (((ch) << 2) + 2))) argument
914 void ald_timer_oc_start(ald_timer_handle_t *hperh, ald_timer_channel_t ch);
915 void ald_timer_oc_stop(ald_timer_handle_t *hperh, ald_timer_channel_t ch);
933 void ald_timer_pwm_stop(ald_timer_handle_t *hperh, ald_timer_channel_t ch);
953 void ald_timer_ic_start(ald_timer_handle_t *hperh, ald_timer_channel_t ch);
[all …]
/bsp/fujitsu/mb9x/mb9bf500r/CMSIS/
A Dstart_rvds.S63 DCD INT0_7_Handler ; 4: External Interrupt Request ch.0 to ch.7
64 DCD INT8_15_Handler ; 5: External Interrupt Request ch.8 to ch.15
90 DCD BT_IRQHandler ; 31: Base Timer ch.0 to ch.7
91 DCD CAN0_IRQHandler ; 32: CAN ch.0
92 DCD CAN1_IRQHandler ; 33: CAN ch.1
97 DCD DMAC0_Handler ; 38: DMAC ch.0
98 DCD DMAC1_Handler ; 39: DMAC ch.1
99 DCD DMAC2_Handler ; 40: DMAC ch.2
100 DCD DMAC3_Handler ; 41: DMAC ch.3
101 DCD DMAC4_Handler ; 42: DMAC ch.4
[all …]
/bsp/fujitsu/mb9x/mb9bf506r/libraries/Device/FUJISTU/MB9BF50x/Source/ARM/
A Dstartup_mb9bf50x.S92 DCD INT0_7_Handler ; 4: External Interrupt Request ch.0 to ch.7
93 DCD INT8_15_Handler ; 5: External Interrupt Request ch.8 to ch.15
119 DCD BT_IRQHandler ; 31: Base Timer ch.0 to ch.7
120 DCD CAN0_IRQHandler ; 32: CAN ch.0
121 DCD CAN1_IRQHandler ; 33: CAN ch.1
126 DCD DMAC0_Handler ; 38: DMAC ch.0
127 DCD DMAC1_Handler ; 39: DMAC ch.1
128 DCD DMAC2_Handler ; 40: DMAC ch.2
129 DCD DMAC3_Handler ; 41: DMAC ch.3
130 DCD DMAC4_Handler ; 42: DMAC ch.4
[all …]
/bsp/CME_M7/StdPeriph_Driver/inc/
A Dcmem7_retarget.h48 uint8_t ch = c; in fputc() local
50 ch = '\r'; in fputc()
51 while (0 == UART_Write(PRINT_UART, 1, &ch)); in fputc()
52 ch = '\n'; in fputc()
55 while (0 == UART_Write(PRINT_UART, 1, &ch)) ; in fputc()
56 return ch; in fputc()
61 uint8_t ch; in fgetc() local
63 while (0 == UART_Read(PRINT_UART, 1, &ch)) ; in fgetc()
64 return ch; in fgetc()
/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/
A Dald_timer.h199 timer_active_channel_t ch; /**< Active channel */ member
457 timer_channel_config_t ch[3]; /**< Configure of channel */ member
631 #define TIMER_CCx_ENABLE(handle, ch) (((ch) == TIMER_CHANNEL_4) ? \ argument
643 #define TIMER_CCx_DISABLE(handle, ch) (((ch) == TIMER_CHANNEL_4) ? \ argument
654 #define TIMER_CCxN_ENABLE(handle, ch) ((handle)->perh->CCEP |= (1 << (((ch) << 2) + 2))) argument
664 #define TIMER_CCxN_DISABLE(handle, ch) ((handle)->perh->CCEP &= ~(1 << (((ch) << 2) + 2))) argument
966 void ald_timer_oc_start(timer_handle_t *hperh, timer_channel_t ch);
967 void ald_timer_oc_stop(timer_handle_t *hperh, timer_channel_t ch);
985 void ald_timer_pwm_stop(timer_handle_t *hperh, timer_channel_t ch);
1005 void ald_timer_ic_start(timer_handle_t *hperh, timer_channel_t ch);
[all …]
/bsp/wch/arm/ch579m/libraries/StdPeriphDriver/
A DCH57x_pwm.c73 void PWMX_ACTOUT( UINT8 ch, UINT8 da, PWMX_PolarTypeDef pr, UINT8 s) in PWMX_ACTOUT() argument
77 if(s == DISABLE) R8_PWM_OUT_EN &= ~(ch); in PWMX_ACTOUT()
80 (pr)?(R8_PWM_POLAR|=(ch)):(R8_PWM_POLAR&=~(ch)); in PWMX_ACTOUT()
83 if((ch>>i)&1) *((PUINT8V)((&R8_PWM4_DATA)+i)) = da; in PWMX_ACTOUT()
85 R8_PWM_OUT_EN |= (ch); in PWMX_ACTOUT()
102 void PWMX_AlterOutCfg( UINT8 ch, UINT8 s) in PWMX_AlterOutCfg() argument
104 if(s == DISABLE) R8_PWM_CONFIG &= ~(ch); in PWMX_AlterOutCfg()
105 else R8_PWM_CONFIG |= (ch); in PWMX_AlterOutCfg()

Completed in 687 milliseconds

12345678910>>...30