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/bsp/renesas/ra4e2-eco/ra/fsp/src/bsp/mcu/all/
A Dbsp_module_stop.h111 #define BSP_MSTP_BIT_FSP_IP_AGT(channel) (1U << (3U - channel));
117 #define BSP_MSTP_BIT_FSP_IP_POEG(channel) (1U << (14U - channel));
132 #define BSP_MSTP_BIT_FSP_IP_AGT(channel) (1U << (3U - channel)); argument
143 #define BSP_MSTP_BIT_FSP_IP_AGT(channel) (1U << (5U - channel));
147 #define BSP_MSTP_BIT_FSP_IP_GPT(channel) (1U << (31 - channel));
153 #define BSP_MSTP_BIT_FSP_IP_AGT(channel) (1U << (5U - channel));
163 #define BSP_MSTP_BIT_FSP_IP_ULPT(channel) (1U << (9U - channel)); argument
167 #define BSP_MSTP_BIT_FSP_IP_GPT(channel) (1U << (31 - channel));
179 #define BSP_MSTP_BIT_FSP_IP_KEY(channel) (1U << (4U - channel));
204 #define BSP_MSTP_BIT_FSP_IP_CAN(channel) (1U << (2U - channel)); argument
[all …]
/bsp/renesas/ra6e2-fpb/ra/fsp/src/bsp/mcu/all/
A Dbsp_module_stop.h111 #define BSP_MSTP_BIT_FSP_IP_AGT(channel) (1U << (3U - channel));
117 #define BSP_MSTP_BIT_FSP_IP_POEG(channel) (1U << (14U - channel));
132 #define BSP_MSTP_BIT_FSP_IP_AGT(channel) (1U << (3U - channel)); argument
143 #define BSP_MSTP_BIT_FSP_IP_AGT(channel) (1U << (5U - channel));
147 #define BSP_MSTP_BIT_FSP_IP_GPT(channel) (1U << (31 - channel));
153 #define BSP_MSTP_BIT_FSP_IP_AGT(channel) (1U << (5U - channel));
163 #define BSP_MSTP_BIT_FSP_IP_ULPT(channel) (1U << (9U - channel)); argument
167 #define BSP_MSTP_BIT_FSP_IP_GPT(channel) (1U << (31 - channel));
179 #define BSP_MSTP_BIT_FSP_IP_KEY(channel) (1U << (4U - channel));
204 #define BSP_MSTP_BIT_FSP_IP_CAN(channel) (1U << (2U - channel)); argument
[all …]
/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/all/
A Dbsp_module_stop.h81 #define BSP_MSTP_BIT_FSP_IP_AGT(channel) (1U << (3U - channel));
92 #define BSP_MSTP_BIT_FSP_IP_AGT(channel) (1U << (3U - channel)); argument
95 #define BSP_MSTP_BIT_FSP_IP_GPT(channel) (1U << (31 - channel));
97 #define BSP_MSTP_BIT_FSP_IP_AGT(channel) (1U << (5U - channel));
104 #define BSP_MSTP_BIT_FSP_IP_ULPT(channel) (1U << (9U - channel)); argument
107 #define BSP_MSTP_BIT_FSP_IP_GPT(channel) (1U << (31 - channel));
110 … channel) ? (1U << (3U - channel)) : (1U << (15U - (channel - 4U))));
112 #define BSP_MSTP_BIT_FSP_IP_KEY(channel) (1U << (4U - channel));
123 #define BSP_MSTP_BIT_FSP_IP_CAN(channel) (1U << (2U - channel)); argument
129 #define BSP_MSTP_BIT_FSP_IP_IRDA(channel) (1U << (5U - channel)); argument
[all …]
/bsp/renesas/ra4m2-eco/ra/fsp/src/bsp/mcu/all/
A Dbsp_module_stop.h73 #define BSP_MSTP_BIT_FSP_IP_AGT(channel) (1U << (3U - channel));
82 #define BSP_MSTP_BIT_FSP_IP_AGT(channel) (1U << (3U - channel)); argument
85 #define BSP_MSTP_BIT_FSP_IP_GPT(channel) (1U << (31 - channel));
87 #define BSP_MSTP_BIT_FSP_IP_AGT(channel) (1U << (5U - channel));
94 #define BSP_MSTP_BIT_FSP_IP_ULPT(channel) (1U << (9U - channel)); argument
97 #define BSP_MSTP_BIT_FSP_IP_GPT(channel) (1U << (31 - channel));
100 … channel) ? (1U << (3U - channel)) : (1U << (15U - (channel - 4U))));
102 #define BSP_MSTP_BIT_FSP_IP_KEY(channel) (1U << (4U - channel));
113 #define BSP_MSTP_BIT_FSP_IP_CAN(channel) (1U << (2U - channel)); argument
119 #define BSP_MSTP_BIT_FSP_IP_IRDA(channel) (1U << (5U - channel)); argument
[all …]
/bsp/renesas/ra8m1-ek/ra/fsp/src/bsp/mcu/all/
A Dbsp_module_stop.h101 #define BSP_MSTP_BIT_FSP_IP_AGT(channel) (1U << (3U - channel));
112 #define BSP_MSTP_BIT_FSP_IP_AGT(channel) (1U << (3U - channel)); argument
115 #define BSP_MSTP_BIT_FSP_IP_GPT(channel) (1U << (31 - channel));
117 #define BSP_MSTP_BIT_FSP_IP_AGT(channel) (1U << (5U - channel));
124 #define BSP_MSTP_BIT_FSP_IP_ULPT(channel) (1U << (9U - channel)); argument
127 #define BSP_MSTP_BIT_FSP_IP_GPT(channel) (1U << (31 - channel));
130 … channel) ? (1U << (3U - channel)) : (1U << (15U - (channel - 4U))));
132 #define BSP_MSTP_BIT_FSP_IP_KEY(channel) (1U << (4U - channel));
143 #define BSP_MSTP_BIT_FSP_IP_CAN(channel) (1U << (2U - channel)); argument
149 #define BSP_MSTP_BIT_FSP_IP_IRDA(channel) (1U << (5U - channel)); argument
[all …]
/bsp/renesas/ra6m3-hmi-board/ra/fsp/src/bsp/mcu/all/
A Dbsp_module_stop.h101 #define BSP_MSTP_BIT_FSP_IP_AGT(channel) (1U << (3U - channel));
112 #define BSP_MSTP_BIT_FSP_IP_AGT(channel) (1U << (3U - channel)); argument
115 #define BSP_MSTP_BIT_FSP_IP_GPT(channel) (1U << (31 - channel));
117 #define BSP_MSTP_BIT_FSP_IP_AGT(channel) (1U << (5U - channel));
124 #define BSP_MSTP_BIT_FSP_IP_ULPT(channel) (1U << (9U - channel)); argument
127 #define BSP_MSTP_BIT_FSP_IP_GPT(channel) (1U << (31 - channel));
130 … channel) ? (1U << (3U - channel)) : (1U << (15U - (channel - 4U))));
132 #define BSP_MSTP_BIT_FSP_IP_KEY(channel) (1U << (4U - channel));
143 #define BSP_MSTP_BIT_FSP_IP_CAN(channel) (1U << (2U - channel)); argument
149 #define BSP_MSTP_BIT_FSP_IP_IRDA(channel) (1U << (5U - channel)); argument
[all …]
/bsp/renesas/ra8d1-ek/ra/fsp/src/bsp/mcu/all/
A Dbsp_module_stop.h101 #define BSP_MSTP_BIT_FSP_IP_AGT(channel) (1U << (3U - channel));
112 #define BSP_MSTP_BIT_FSP_IP_AGT(channel) (1U << (3U - channel)); argument
115 #define BSP_MSTP_BIT_FSP_IP_GPT(channel) (1U << (31 - channel));
117 #define BSP_MSTP_BIT_FSP_IP_AGT(channel) (1U << (5U - channel));
124 #define BSP_MSTP_BIT_FSP_IP_ULPT(channel) (1U << (9U - channel)); argument
127 #define BSP_MSTP_BIT_FSP_IP_GPT(channel) (1U << (31 - channel));
130 … channel) ? (1U << (3U - channel)) : (1U << (15U - (channel - 4U))));
132 #define BSP_MSTP_BIT_FSP_IP_KEY(channel) (1U << (4U - channel));
143 #define BSP_MSTP_BIT_FSP_IP_CAN(channel) (1U << (2U - channel)); argument
149 #define BSP_MSTP_BIT_FSP_IP_IRDA(channel) (1U << (5U - channel)); argument
[all …]
/bsp/renesas/ra8d1-vision-board/ra/fsp/src/bsp/mcu/all/
A Dbsp_module_stop.h101 #define BSP_MSTP_BIT_FSP_IP_AGT(channel) (1U << (3U - channel));
112 #define BSP_MSTP_BIT_FSP_IP_AGT(channel) (1U << (3U - channel)); argument
115 #define BSP_MSTP_BIT_FSP_IP_GPT(channel) (1U << (31 - channel));
117 #define BSP_MSTP_BIT_FSP_IP_AGT(channel) (1U << (5U - channel));
124 #define BSP_MSTP_BIT_FSP_IP_ULPT(channel) (1U << (9U - channel)); argument
127 #define BSP_MSTP_BIT_FSP_IP_GPT(channel) (1U << (31 - channel));
130 … channel) ? (1U << (3U - channel)) : (1U << (15U - (channel - 4U))));
132 #define BSP_MSTP_BIT_FSP_IP_KEY(channel) (1U << (4U - channel));
143 #define BSP_MSTP_BIT_FSP_IP_CAN(channel) (1U << (2U - channel)); argument
149 #define BSP_MSTP_BIT_FSP_IP_IRDA(channel) (1U << (5U - channel)); argument
[all …]
/bsp/renesas/ra6m3-ek/ra/fsp/src/bsp/mcu/all/
A Dbsp_module_stop.h73 #define BSP_MSTP_BIT_FSP_IP_AGT(channel) (1U << (3U - channel));
81 #define BSP_MSTP_BIT_FSP_IP_AGT(channel) (1U << (3U - channel)); argument
85 #define BSP_MSTP_BIT_FSP_IP_POEG(channel) (1U << (14U - channel)); argument
88 #define BSP_MSTP_BIT_FSP_IP_GPT(channel) (1U << (31 - channel));
91 … channel) ? (1U << (3U - channel)) : (1U << (15U - (channel - 4U))));
93 #define BSP_MSTP_BIT_FSP_IP_KEY(channel) (1U << (4U - channel));
104 #define BSP_MSTP_BIT_FSP_IP_CAN(channel) (1U << (2U - channel)); argument
108 #define BSP_MSTP_BIT_FSP_IP_IRDA(channel) (1U << (5U - channel)); argument
110 #define BSP_MSTP_BIT_FSP_IP_QSPI(channel) (1U << (6U - channel)); argument
112 #define BSP_MSTP_BIT_FSP_IP_IIC(channel) (1U << (9U - channel)); argument
[all …]
/bsp/renesas/ra6m4-cpk/ra/fsp/src/bsp/mcu/all/
A Dbsp_module_stop.h73 #define BSP_MSTP_BIT_FSP_IP_AGT(channel) (1U << (3U - channel));
81 #define BSP_MSTP_BIT_FSP_IP_AGT(channel) (1U << (3U - channel)); argument
85 #define BSP_MSTP_BIT_FSP_IP_POEG(channel) (1U << (14U - channel)); argument
88 #define BSP_MSTP_BIT_FSP_IP_GPT(channel) (1U << (31 - channel));
91 … channel) ? (1U << (3U - channel)) : (1U << (15U - (channel - 4U))));
93 #define BSP_MSTP_BIT_FSP_IP_KEY(channel) (1U << (4U - channel));
104 #define BSP_MSTP_BIT_FSP_IP_CAN(channel) (1U << (2U - channel)); argument
108 #define BSP_MSTP_BIT_FSP_IP_IRDA(channel) (1U << (5U - channel)); argument
110 #define BSP_MSTP_BIT_FSP_IP_QSPI(channel) (1U << (6U - channel)); argument
112 #define BSP_MSTP_BIT_FSP_IP_IIC(channel) (1U << (9U - channel)); argument
[all …]
/bsp/renesas/ra6m4-iot/ra/fsp/src/bsp/mcu/all/
A Dbsp_module_stop.h73 #define BSP_MSTP_BIT_FSP_IP_AGT(channel) (1U << (3U - channel));
81 #define BSP_MSTP_BIT_FSP_IP_AGT(channel) (1U << (3U - channel)); argument
85 #define BSP_MSTP_BIT_FSP_IP_POEG(channel) (1U << (14U - channel)); argument
88 #define BSP_MSTP_BIT_FSP_IP_GPT(channel) (1U << (31 - channel));
91 … channel) ? (1U << (3U - channel)) : (1U << (15U - (channel - 4U))));
93 #define BSP_MSTP_BIT_FSP_IP_KEY(channel) (1U << (4U - channel));
104 #define BSP_MSTP_BIT_FSP_IP_CAN(channel) (1U << (2U - channel)); argument
108 #define BSP_MSTP_BIT_FSP_IP_IRDA(channel) (1U << (5U - channel)); argument
110 #define BSP_MSTP_BIT_FSP_IP_QSPI(channel) (1U << (6U - channel)); argument
112 #define BSP_MSTP_BIT_FSP_IP_IIC(channel) (1U << (9U - channel)); argument
[all …]
/bsp/renesas/ra2l1-cpk/ra/fsp/src/bsp/mcu/all/
A Dbsp_module_stop.h73 #define BSP_MSTP_BIT_FSP_IP_AGT(channel) (1U << (3U - channel));
81 #define BSP_MSTP_BIT_FSP_IP_AGT(channel) (1U << (3U - channel)); argument
85 #define BSP_MSTP_BIT_FSP_IP_POEG(channel) (1U << (14U - channel)); argument
88 #define BSP_MSTP_BIT_FSP_IP_GPT(channel) (1U << (31 - channel));
91 … channel) ? (1U << (3U - channel)) : (1U << (15U - (channel - 4U))));
93 #define BSP_MSTP_BIT_FSP_IP_KEY(channel) (1U << (4U - channel));
104 #define BSP_MSTP_BIT_FSP_IP_CAN(channel) (1U << (2U - channel)); argument
108 #define BSP_MSTP_BIT_FSP_IP_IRDA(channel) (1U << (5U - channel)); argument
110 #define BSP_MSTP_BIT_FSP_IP_QSPI(channel) (1U << (6U - channel)); argument
112 #define BSP_MSTP_BIT_FSP_IP_IIC(channel) (1U << (9U - channel)); argument
[all …]
/bsp/renesas/rzt2m_rsk/rzt/fsp/src/bsp/mcu/all/
A Dbsp_module_stop.h76 #define BSP_MSTP_BIT_FSP_IP_XSPI(channel) (1U << (4U + channel)); argument
80 #define BSP_MSTP_BIT_FSP_IP_SCI(channel) ((4U >= channel) ? (1U << (8U + channel)) : (1U)… argument
81 #define BSP_MSTP_DMY_FSP_IP_SCI(channel) (0 >= channel) ? R_SCI0->RDR : ((1 >= channel) ?… argument
96 #define BSP_MSTP_BIT_FSP_IP_IIC(channel) ((1U >= channel) ? (1U << (0U + channel)) : (1U … argument
97 #define BSP_MSTP_DMY_FSP_IP_IIC(channel) (0 >= channel) ? R_IIC0->ICCR1 : ((1 >= channel)… argument
101 #define BSP_MSTP_BIT_FSP_IP_SPI(channel) ((2U >= channel) ? (1U << (4U + channel)) : (1U … argument
102 #define BSP_MSTP_DMY_FSP_IP_SPI(channel) (0 >= channel) ? R_SPI0->SPCKD : ((1 >= channel)… argument
112 #define BSP_MSTP_BIT_FSP_IP_GPT(channel) ((6U >= channel) ? (1U << (1U)) : ((13U >= chann… argument
123 #define BSP_MSTP_BIT_FSP_IP_ADC12(channel) (1U << (6U + channel)); argument
127 #define BSP_MSTP_BIT_FSP_IP_DSMIF(channel) (1U << (0U + channel)); argument
[all …]
/bsp/renesas/rzn2l_etherkit/rzn/fsp/src/bsp/mcu/all/
A Dbsp_module_stop.h76 #define BSP_MSTP_BIT_FSP_IP_XSPI(channel) (1U << (4U + channel)); argument
80 #define BSP_MSTP_BIT_FSP_IP_SCI(channel) ((4U >= channel) ? (1U << (8U + channel)) : (1U)… argument
81 #define BSP_MSTP_DMY_FSP_IP_SCI(channel) (0 >= channel) ? R_SCI0->RDR : ((1 >= channel) ?… argument
96 #define BSP_MSTP_BIT_FSP_IP_IIC(channel) ((1U >= channel) ? (1U << (0U + channel)) : (1U … argument
97 #define BSP_MSTP_DMY_FSP_IP_IIC(channel) (0 >= channel) ? R_IIC0->ICCR1 : ((1 >= channel)… argument
101 #define BSP_MSTP_BIT_FSP_IP_SPI(channel) ((2U >= channel) ? (1U << (4U + channel)) : (1U … argument
102 #define BSP_MSTP_DMY_FSP_IP_SPI(channel) (0 >= channel) ? R_SPI0->SPCKD : ((1 >= channel)… argument
112 #define BSP_MSTP_BIT_FSP_IP_GPT(channel) ((6U >= channel) ? (1U << (1U)) : ((13U >= chann… argument
123 #define BSP_MSTP_BIT_FSP_IP_ADC12(channel) (1U << (6U + channel)); argument
127 #define BSP_MSTP_BIT_FSP_IP_DSMIF(channel) (1U << (0U + channel)); argument
[all …]
/bsp/renesas/rzn2l_rsk/rzn/fsp/src/bsp/mcu/all/
A Dbsp_module_stop.h76 #define BSP_MSTP_BIT_FSP_IP_XSPI(channel) (1U << (4U + channel)); argument
80 #define BSP_MSTP_BIT_FSP_IP_SCI(channel) ((4U >= channel) ? (1U << (8U + channel)) : (1U)… argument
81 #define BSP_MSTP_DMY_FSP_IP_SCI(channel) (0 >= channel) ? R_SCI0->RDR : ((1 >= channel) ?… argument
96 #define BSP_MSTP_BIT_FSP_IP_IIC(channel) ((1U >= channel) ? (1U << (0U + channel)) : (1U … argument
97 #define BSP_MSTP_DMY_FSP_IP_IIC(channel) (0 >= channel) ? R_IIC0->ICCR1 : ((1 >= channel)… argument
101 #define BSP_MSTP_BIT_FSP_IP_SPI(channel) ((2U >= channel) ? (1U << (4U + channel)) : (1U … argument
102 #define BSP_MSTP_DMY_FSP_IP_SPI(channel) (0 >= channel) ? R_SPI0->SPCKD : ((1 >= channel)… argument
112 #define BSP_MSTP_BIT_FSP_IP_GPT(channel) ((6U >= channel) ? (1U << (1U)) : ((13U >= chann… argument
123 #define BSP_MSTP_BIT_FSP_IP_ADC12(channel) (1U << (6U + channel)); argument
127 #define BSP_MSTP_BIT_FSP_IP_DSMIF(channel) (1U << (0U + channel)); argument
[all …]
/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/
A Dbflb_acomp.c107 *channel = AON_ACOMP_CHAN_ADC0; in bflb_acomp_gpio_2_chanid()
109 *channel = AON_ACOMP_CHAN_ADC1; in bflb_acomp_gpio_2_chanid()
111 *channel = AON_ACOMP_CHAN_ADC2; in bflb_acomp_gpio_2_chanid()
113 *channel = AON_ACOMP_CHAN_ADC3; in bflb_acomp_gpio_2_chanid()
115 *channel = AON_ACOMP_CHAN_ADC4; in bflb_acomp_gpio_2_chanid()
117 *channel = AON_ACOMP_CHAN_ADC5; in bflb_acomp_gpio_2_chanid()
119 *channel = AON_ACOMP_CHAN_ADC6; in bflb_acomp_gpio_2_chanid()
127 *channel = AON_ACOMP_CHAN_ADC0; in bflb_acomp_gpio_2_chanid()
129 *channel = AON_ACOMP_CHAN_ADC1; in bflb_acomp_gpio_2_chanid()
131 *channel = AON_ACOMP_CHAN_ADC2; in bflb_acomp_gpio_2_chanid()
[all …]
/bsp/wch/arm/Libraries/ch32_drivers/
A Ddrv_pwm_ch32f20x.c32 rt_uint8_t channel[4]; member
48 .channel[0] = 0xFF,
54 .channel[1] = 0xFF,
60 .channel[2] = 0xFF,
66 .channel[3] = 0xFF,
78 .channel[0] = 0xFF,
84 .channel[1] = 0xFF,
90 .channel[2] = 0xFF,
96 .channel[3] = 0xFF,
108 .channel[0] = 0xFF,
[all …]
/bsp/apm32/libraries/APM32E10x_Library/APM32E10x_StdPeriphDriver/src/
A Dapm32e10x_dma.c53 channel->CHCFG = 0; in DMA_Reset()
54 channel->CHNDATA = 0; in DMA_Reset()
55 channel->CHMADDR = 0; in DMA_Reset()
56 channel->CHPADDR = 0; in DMA_Reset()
58 if(channel == DMA1_Channel1) in DMA_Reset()
62 else if(channel == DMA1_Channel2) in DMA_Reset()
66 else if(channel == DMA1_Channel3) in DMA_Reset()
198 channel->CHNDATA = dataNumber; in DMA_ConfigDataNumber()
212 return channel->CHNDATA; in DMA_ReadDataNumber()
232 channel->CHCFG |= interrupt; in DMA_EnableInterrupt()
[all …]
/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/
A Dapm32f10x_dma.c50 void DMA_Reset(DMA_Channel_T* channel) in DMA_Reset() argument
53 channel->CHCFG = 0; in DMA_Reset()
54 channel->CHNDATA = 0; in DMA_Reset()
55 channel->CHMADDR = 0; in DMA_Reset()
56 channel->CHPADDR = 0; in DMA_Reset()
58 if (channel == DMA1_Channel1) in DMA_Reset()
168 channel->CHCFG_B.CHEN = ENABLE; in DMA_Enable()
198 channel->CHNDATA = dataNumber; in DMA_ConfigDataNumber()
212 return channel->CHNDATA; in DMA_ReadDataNumber()
232 channel->CHCFG |= interrupt; in DMA_EnableInterrupt()
[all …]
/bsp/apm32/libraries/APM32S10x_Library/APM32S10x_StdPeriphDriver/src/
A Dapm32s10x_dma.c48 void DMA_Reset(DMA_Channel_T* channel) in DMA_Reset() argument
51 channel->CHCFG = 0; in DMA_Reset()
52 channel->CHNDATA = 0; in DMA_Reset()
53 channel->CHMADDR = 0; in DMA_Reset()
54 channel->CHPADDR = 0; in DMA_Reset()
56 if (channel == DMA1_Channel1) in DMA_Reset()
142 channel->CHCFG_B.CHEN = ENABLE; in DMA_Enable()
168 channel->CHNDATA = dataNumber; in DMA_ConfigDataNumber()
180 return channel->CHNDATA; in DMA_ReadDataNumber()
198 channel->CHCFG |= interrupt; in DMA_EnableInterrupt()
[all …]
/bsp/apm32/libraries/APM32F0xx_Library/APM32F0xx_StdPeriphDriver/src/
A Dapm32f0xx_dma.c85 void DMA_Reset(DMA_CHANNEL_T* channel) in DMA_Reset() argument
87 channel->CHCFG_B.CHEN = 0; in DMA_Reset()
88 channel->CHCFG = 0; in DMA_Reset()
89 channel->CHNDATA = 0; in DMA_Reset()
90 channel->CHPADDR = 0; in DMA_Reset()
91 channel->CHMADDR = 0; in DMA_Reset()
93 if (channel == DMA1_CHANNEL_1) in DMA_Reset()
97 else if (channel == DMA1_CHANNEL_2) in DMA_Reset()
101 else if (channel == DMA1_CHANNEL_3) in DMA_Reset()
105 else if (channel == DMA1_CHANNEL_4) in DMA_Reset()
[all …]
/bsp/wch/risc-v/Libraries/ch32_drivers/
A Ddrv_pwm.c107 if (channel == TIM_Channel_1) in ch32_pwm_io_init()
117 if (channel == TIM_Channel_2) in ch32_pwm_io_init()
127 if (channel == TIM_Channel_3) in ch32_pwm_io_init()
137 if (channel == TIM_Channel_4) in ch32_pwm_io_init()
154 if (channel == TIM_Channel_1) in ch32_pwm_io_init()
164 if (channel == TIM_Channel_2) in ch32_pwm_io_init()
174 if (channel == TIM_Channel_3) in ch32_pwm_io_init()
184 if (channel == TIM_Channel_4) in ch32_pwm_io_init()
202 if (channel == TIM_Channel_1) in ch32_pwm_io_init()
212 if (channel == TIM_Channel_2) in ch32_pwm_io_init()
[all …]
/bsp/mm32/libraries/MM32F3270_HAL/MM32F3270_HAL_Driver/Src/
A Dhal_dac.c50 if(channel == DAC_CHN_1) in DAC_GetData()
54 else if (channel == DAC_CHN_2) in DAC_GetData()
209 if (channel == DAC_CHN_1) in DAC_PutData8bRightAlign()
213 else if (channel == DAC_CHN_2) in DAC_PutData8bRightAlign()
222 if (channel == DAC_CHN_1) in DAC_PutData12bLeftAlign()
226 else if (channel == DAC_CHN_2) in DAC_PutData12bLeftAlign()
235 if (channel == DAC_CHN_1) in DAC_PutData12bRightAlign()
239 else if (channel == DAC_CHN_2) in DAC_PutData12bRightAlign()
267 if (channel == DAC_CHN_1) in DAC_GetData8bRegAddr()
283 if (channel == DAC_CHN_1) in DAC_GetData12bLeftRegAddr()
[all …]
/bsp/at32/libraries/rt_drivers/
A Ddrv_pwm.c30 rt_uint8_t channel; member
209 rt_uint32_t channel = configuration->channel; in drv_pwm_enable() local
297 rt_uint32_t channel = configuration->channel; in drv_pwm_get() local
338 if(channel == 1) in drv_pwm_get()
340 if(channel == 2) in drv_pwm_get()
342 if(channel == 3) in drv_pwm_get()
344 if(channel == 4) in drv_pwm_get()
412 channel = configuration->channel; in drv_pwm_set()
413 if(channel == 1) in drv_pwm_set()
545 channel = configuration->channel; in drv_pwm_set_pulse()
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/bsp/apm32/libraries/APM32F4xx_Library/APM32F4xx_StdPeriphDriver/src/
A Dapm32f4xx_dac.c80 temp1 |= temp2 << channel; in DAC_Config()
112 if (channel == DAC_CHANNEL_1) in DAC_Enable()
134 if (channel == DAC_CHANNEL_1) in DAC_Disable()
156 if (channel == DAC_CHANNEL_1) in DAC_DMA_Enable()
178 if (channel == DAC_CHANNEL_1) in DAC_DMA_Disable()
200 if (channel == DAC_CHANNEL_1) in DAC_EnableSoftwareTrigger()
222 if (channel == DAC_CHANNEL_1) in DAC_DisableSoftwareTrigger()
276 DAC->CTRL |= wave << channel; in DAC_EnableWaveGeneration()
416 if (channel == DAC_CHANNEL_1) in DAC_EnableInterrupt()
438 if (channel == DAC_CHANNEL_1) in DAC_DisableInterrupt()
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