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Searched refs:clk (Results 1 – 25 of 204) sorted by relevance

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/bsp/allwinner/libraries/sunxi-hal/hal/source/ccmu/sunxi-ng/
A Dclk.c23 struct clk *clk = NULL; in clk_get() local
32 clk = core->clk; in clk_get()
38 hal_clk_status_t clk_put(struct clk *clk) in clk_put() argument
40 if (!clk) in clk_put()
51 hal_clk_status_t clk_is_enabled(struct clk *clk) in clk_is_enabled() argument
55 if (clk) in clk_is_enabled()
62 hal_clk_status_t clk_prepare_enable(struct clk *clk) in clk_prepare_enable() argument
72 hal_clk_status_t clk_disable_unprepare(struct clk *clk) in clk_disable_unprepare() argument
81 struct clk *clk_get_parent(struct clk *clk) in clk_get_parent() argument
102 p_clk = (struct clk *)malloc(sizeof(*clk)); in clk_get_parent()
[all …]
A Dclk.h51 struct clk *clk_get(hal_clk_type_t type, hal_clk_id_t id);
53 hal_clk_status_t clk_put(struct clk *clk);
66 hal_clk_status_t clk_get_rate(struct clk *clk, u32 *rate);
82 hal_clk_status_t clk_set_rate(struct clk *clk, u32 rate);
96 hal_clk_status_t clk_recalc_rate(struct clk *clk, u32 *prate);
111 hal_clk_status_t clk_round_rate(struct clk *clk, u32 rate, u32 *prate);
127 hal_clk_status_t clk_is_enabled(struct clk *clk);
144 hal_clk_status_t clk_prepare_enable(struct clk *clk);
159 hal_clk_status_t clk_disable_unprepare(struct clk *clk);
172 struct clk *clk_get_parent(struct clk *clk);
[all …]
A DMakefile4 obj-y += clk.o
19 obj-y += clk-fixed-factor.o
20 obj-y += clk-fixed-rate.o
21 obj-y += clk-divider.o
/bsp/allwinner/libraries/sunxi-hal/hal/source/ccmu/
A Dhal_clk.c49 return clk_put(clk); in hal_clock_put()
55 return clk_set_parent(clk, parent); in hal_clk_set_parent()
61 return clk_get_parent(clk); in hal_clk_get_parent()
64 u32 hal_clk_recalc_rate(hal_clk_t clk) in hal_clk_recalc_rate() argument
69 clk_recalc_rate(clk, &rate); in hal_clk_recalc_rate()
84 u32 hal_clk_get_rate(hal_clk_t clk) in hal_clk_get_rate() argument
89 clk_get_rate(clk, &rate); in hal_clk_get_rate()
99 ret = clk_set_rate(clk, rate); in hal_clk_set_rate()
107 return clk_is_enabled(clk); in hal_clock_is_enabled()
115 ret = clk_prepare_enable(clk); in hal_clock_enable()
[all …]
A Dcommon_ccmu.h47 #define CCMU_TRACE_CLK(tpye, clk) printf("CCMU:trace %s:%d CLK "#tpye" id %d\n",__func__, __LINE_… argument
50 #define CCMU_TRACE_CLK(clk, rate) do{} while(0) argument
104 typedef struct clk *hal_clk_t;
/bsp/allwinner/libraries/sunxi-hal/hal/source/prcm/
A Dclk_compat.c12 return ccu_set_mclk_src(clk, parent) == OK ? in hal_clk_set_parent()
17 hal_clk_id_t hal_clk_get_parent(hal_clk_id_t clk) in hal_clk_get_parent() argument
19 return ccu_get_mclk_src(clk); in hal_clk_get_parent()
22 u32 hal_clk_recalc_rate(hal_clk_id_t clk) in hal_clk_recalc_rate() argument
24 return ccu_get_sclk_freq(clk); in hal_clk_recalc_rate()
27 u32 hal_clk_round_rate(hal_clk_id_t clk, u32 rate) in hal_clk_round_rate() argument
33 u32 hal_clk_get_rate(hal_clk_id_t clk) in hal_clk_get_rate() argument
35 return ccu_get_sclk_freq(clk); in hal_clk_get_rate()
40 return ccu_set_sclk_freq(clk, rate) == OK ? in hal_clk_set_rate()
51 hal_clk_status_t hal_clock_enable(hal_clk_id_t clk) in hal_clock_enable() argument
[all …]
/bsp/allwinner/libraries/sunxi-hal/hal/source/ccmu/sunxi/
A Dclk.c91 if (pclk->clk == clk) in clk_get_core()
102 if (pclk->clk == clk) in clk_get_core()
113 if (pclk->clk == clk) in clk_get_core()
124 if (pclk->clk == clk) in clk_get_core()
148 pclk = clk_get_core(clk); in sunxi_clk_set_parent()
213 pclk = clk_get_core(clk); in sunxi_clk_get_parent()
271 pclk = clk_get_core(clk); in sunxi_clk_disable()
327 pclk = clk_get_core(clk); in sunxi_clk_enabled()
379 pclk = clk_get_core(clk); in sunxi_clk_is_enabled()
423 pclk = clk_get_core(clk); in sunxi_clk_round_rate()
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A Dclk.h43 hal_clk_id_t clk; member
50 hal_clk_id_t clk; member
107 .clk = _clk, \
158 clk_core_pt clk_get_core(hal_clk_id_t clk);
188 hal_clk_status_t clk_get_rate(hal_clk_id_t clk, u32 *rate);
205 hal_clk_status_t clk_set_rate(hal_clk_id_t clk, u32 rate);
219 hal_clk_status_t clk_recalc_rate(hal_clk_id_t clk, u32 *prate);
251 hal_clk_status_t clk_is_enabled(hal_clk_id_t clk);
268 hal_clk_status_t clk_prepare_enable(hal_clk_id_t clk);
284 hal_clk_status_t clk_disable_unprepare(hal_clk_id_t clk);
[all …]
A Dclk_periph.h74 .clk = _clk, \
89 .clk = _clk, \
219 hal_clk_status_t sunxi_clk_periph_get_parent(clk_periph_pt clk, u8 *parent_index);
220 hal_clk_status_t sunxi_clk_periph_set_parent(clk_periph_pt clk, u8 index);
221 hal_clk_status_t sunxi_clk_periph_enable(clk_periph_pt clk);
222 hal_clk_status_t sunxi_clk_periph_is_enabled(clk_periph_pt clk);
223 hal_clk_status_t sunxi_clk_periph_disable(clk_periph_pt clk);
224 hal_clk_status_t sunxi_clk_periph_recalc_rate(clk_periph_pt clk, u32 *rate);
225 u32 sunxi_clk_periph_round_rate(clk_periph_pt clk, u32 rate, u32 prate);
226 hal_clk_status_t sunxi_clk_periph_set_rate(clk_periph_pt clk, u32 rate);
A Dclk_periph.c40 struct sunxi_clk_periph *periph = clk->config; in sunxi_clk_periph_get_parent()
66 struct sunxi_clk_periph *periph = clk->config; in sunxi_clk_periph_set_parent()
175 hal_clk_status_t sunxi_clk_periph_enable(clk_periph_pt clk) in sunxi_clk_periph_enable() argument
183 periph = clk->config; in sunxi_clk_periph_enable()
212 periph = clk->config; in sunxi_clk_periph_is_enabled()
349 periph = clk->config; in sunxi_clk_periph_disable()
375 periph = clk->config; in sunxi_clk_periph_recalc_rate()
377 parent_rate = clk->clk_core.parent_rate; in sunxi_clk_periph_recalc_rate()
417 periph = clk->config; in sunxi_clk_periph_round_rate()
489 periph = clk->config; in sunxi_clk_periph_set_rate()
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A Dclk_factors.c131 factor = clk->factor_data; in sunxi_clk_fators_enable()
202 factor = clk->factor_data; in sunxi_clk_fators_disable()
258 factor = clk->factor_data; in sunxi_clk_fators_is_enabled()
285 factor = clk->factor_data; in sunxi_clk_factors_recalc_rate()
292 parent_rate = clk->clk_core.parent_rate; in sunxi_clk_factors_recalc_rate()
382 factor = clk->factor_data; in sunxi_clk_factors_set_rate()
384 parent_rate = clk->clk_core.parent_rate; in sunxi_clk_factors_set_rate()
399 … CCMU_ERR("clk %d set rate failed! Because cannot get right factors for clk\n", clk->clk_core.clk); in sunxi_clk_factors_set_rate()
460 CCMU_ERR("clk %d wait lock timeout\n", clk->clk_core.clk); in sunxi_clk_factors_set_rate()
497 struct factor_init_data *factor = clk->factor_data; in sunxi_clk_factors_round_rate()
[all …]
/bsp/at91/at91sam9260/platform/
A Dsystem_clock.c16 struct clk { struct
19 struct clk *parent; argument
23 static struct clk clk32k = { argument
37 static struct clk plla = {
44 static struct clk mck = {
58 static struct clk pllb = {
85 struct clk *clk; in clk_get() local
90 clk = (struct clk *)rt_list_entry(list, struct clk, node); in clk_get()
92 return clk; in clk_get()
98 rt_uint32_t clk_get_rate(struct clk *clk) in clk_get_rate() argument
[all …]
/bsp/allwinner/libraries/sunxi-hal/hal/test/ccmu/
A Dtest_ng_ccmu.c34 int is_strict_clk(hal_clk_t clk) in is_strict_clk() argument
39 if (!strcmp(clk->name, strict_clks[i])) in is_strict_clk()
63 hal_clk_t clk, p_clk; in cmd_test_ng_ccmu() local
79 clk = hal_clock_get(clk_type, clk_id); in cmd_test_ng_ccmu()
81 clk_status = hal_clock_is_enabled(clk); in cmd_test_ng_ccmu()
84 hal_clock_enable(clk); in cmd_test_ng_ccmu()
88 if (is_strict_clk(clk)) in cmd_test_ng_ccmu()
91 p_clk = hal_clk_get_parent(clk); in cmd_test_ng_ccmu()
97 old_rate = hal_clk_get_rate(clk); in cmd_test_ng_ccmu()
101 hal_clk_set_rate(clk, old_rate); in cmd_test_ng_ccmu()
[all …]
/bsp/at91/at91sam9g45/platform/
A Dsystem_clock.c16 struct clk { struct
19 struct clk *parent; argument
23 static struct clk clk32k = { argument
37 static struct clk plla = {
44 static struct clk mck = {
51 static struct clk upllck = {
71 struct clk *clk; in clk_get() local
76 clk = (struct clk *)rt_list_entry(list, struct clk, node); in clk_get()
78 return clk; in clk_get()
84 rt_uint32_t clk_get_rate(struct clk *clk) in clk_get_rate() argument
[all …]
/bsp/allwinner_tina/drivers/
A Ddrv_clock.c213 if (clk == 0) in cpu_set_pll_clk()
243 int n_temp = clk; in audio_set_pll_clk()
246 if ((clk > 200000000) || (clk < 20000000)) in audio_set_pll_clk()
249 if (clk == 0) in audio_set_pll_clk()
267 n = clk / n_temp; in audio_set_pll_clk()
287 int n_temp = clk; in video_set_pll_clk()
290 if ((clk > 600000000) || (clk < 30000000)) in video_set_pll_clk()
293 if (clk == 0) in video_set_pll_clk()
335 if ((clk > 600000000) || (clk < 30000000)) in ve_set_pll_clk()
338 if (clk == 0) in ve_set_pll_clk()
[all …]
/bsp/dm365/platform/
A Ddm365.c64 struct clk { struct
67 struct clk *parent; argument
161 struct clk *clk; in clk_get() local
166 clk = (struct clk *)rt_list_entry(list, struct clk, node); in clk_get()
168 return clk; in clk_get()
174 rt_uint32_t clk_get_rate(struct clk *clk) in clk_get_rate() argument
180 rate = clk->rate_hz; in clk_get_rate()
183 clk = clk->parent; in clk_get_rate()
188 void clk_register(struct clk *clk) in clk_register() argument
195 struct clk *clkp; in davinci_register_clks()
[all …]
/bsp/allwinner/libraries/sunxi-hal/include/hal/
A Dhal_clk.h74 #define CCMU_TRACE_CLK(tpye, clk) printf("CCMU:trace %s:%d CLK "#tpye" id %d\n",__func__, __LINE_… argument
77 #define CCMU_TRACE_CLK(clk, rate) do{} while(0) argument
105 hal_clk_status_t hal_clock_put(hal_clk_t clk);
121 hal_clk_status_t hal_clock_is_enabled(hal_clk_t clk);
137 hal_clk_status_t hal_clock_enable(hal_clk_t clk);
153 hal_clk_status_t hal_clock_disable(hal_clk_t clk);
167 u32 hal_clk_recalc_rate(hal_clk_t clk);
182 u32 hal_clk_round_rate(hal_clk_t clk, u32 rate);
196 u32 hal_clk_get_rate(hal_clk_t clk);
213 hal_clk_status_t hal_clk_set_rate(hal_clk_t clk, u32 rate);
[all …]
/bsp/allwinner/libraries/sunxi-hal/hal/source/disp2/soc/
A Dplatform_resource.c53 g_clk_no[i].clk = hal_clock_get(HAL_SUNXI_CCU, g_clk_no[i].clk_id); in plat_get_clk()
69 s32 plat_get_clk_parent(hal_clk_id_t clk, hal_clk_id_t *parent) in plat_get_clk_parent() argument
74 if (g_clk_no[i].clk_id == clk) { in plat_get_clk_parent()
83 s32 plat_get_clk_from_id(hal_clk_id_t clk_id, hal_clk_t *clk, struct reset_control **rst) in plat_get_clk_from_id() argument
89 *clk = g_clk_no[i].clk; in plat_get_clk_from_id()
93 *clk = g_clk_no[i].clk_parent; in plat_get_clk_from_id()
/bsp/k230/drivers/interdrv/sysctl/sysctl_clock/
A Dsysctl_clk.h550 bool sysctl_boot_get_root_clk_bypass(sysctl_clk_node_e clk);
551 void sysctl_boot_set_root_clk_bypass(sysctl_clk_node_e clk, bool enable);
554 bool sysctl_boot_get_root_clk_en(sysctl_clk_node_e clk);
555 void sysctl_boot_set_root_clk_en(sysctl_clk_node_e clk, bool enable);
558 bool sysctl_boot_get_root_clk_lock(sysctl_clk_node_e clk);
561 uint32_t sysctl_boot_get_root_clk_freq(sysctl_clk_node_e clk);
568 bool sysctl_boot_set_root_clk_freq(sysctl_clk_node_e clk, uint32_t fbdiv, uint32_t refdiv, uint32_t…
/bsp/n32/libraries/n32_drivers/
A Ddrv_hwtimer.c169 uint32_t clk; in n32_hwtimer_control() local
174 clk = RCC_ClockFreq.Pclk1Freq; in n32_hwtimer_control()
179 clk = RCC_ClockFreq.Pclk2Freq; in n32_hwtimer_control()
184 clk = clk * 2; in n32_hwtimer_control()
186 pre = (clk / * ((uint32_t *)args)) - 1; in n32_hwtimer_control()
245 uint32_t clk; in n32_hwtimer_init() local
254 clk = RCC_ClockFreq.Pclk1Freq; in n32_hwtimer_init()
259 clk = RCC_ClockFreq.Pclk2Freq; in n32_hwtimer_init()
264 clk = clk * 2; in n32_hwtimer_init()
266 pre = (clk / 10000) - 1; in n32_hwtimer_init()
/bsp/allwinner/libraries/sunxi-hal/hal/source/disp2/disp/de/
A Ddisp_hdmi.c36 struct clk *clk; member
37 struct clk *parent_clk;
90 if (hdmip->clk) { in hdmi_clk_init()
130 struct clk *parent_clk; in hdmi_clk_config()
172 clk_set_rate(hdmip->clk, rate); in hdmi_clk_config()
189 if (hdmip->clk && (!__clk_get_enable_count(hdmip->clk))) { in hdmi_clk_enable()
207 if (hdmip->clk && (__clk_get_enable_count(hdmip->clk))) in hdmi_clk_disable()
208 clk_disable_unprepare(hdmip->clk); in hdmi_clk_disable()
220 if (!hdmip->clk) in disp_hdmi_pad_sel()
223 clk_prepare_enable(hdmip->clk); in disp_hdmi_pad_sel()
[all …]
A Ddisp_tv.h33 struct clk *clk; member
35 struct clk *clk_parent;
/bsp/allwinner/libraries/sunxi-hal/hal/source/usb/host/
A Dsunxi-hci.h372 struct clk *ahb; /* ahb clock handle */
373 struct clk *mod_usb; /* mod_usb otg clock handle */
374 struct clk *mod_usbphy; /* PHY0 clock handle */
375 struct clk *hsic_usbphy; /* hsic clock handle */
376 struct clk *pll_hsic; /* pll_hsic clock handle */
377 struct clk *clk_usbhsic12m; /* pll_hsic clock handle */
379 struct clk *clk_usbohci12m; /* clk_usbohci12m clock handle */
380 struct clk *clk_hoscx2; /* clk_hoscx2 clock handle */
381 struct clk *clk_hosc; /* clk_hosc clock handle */
382 struct clk *clk_losc; /* clk_losc clock handle */
/bsp/rockchip/common/rk_hal/lib/hal/inc/
A Dhal_cru.h133 HAL_Check HAL_CRU_ClkIsEnabled(uint32_t clk);
134 HAL_Status HAL_CRU_ClkEnable(uint32_t clk);
135 HAL_Status HAL_CRU_ClkDisable(uint32_t clk);
137 HAL_Check HAL_CRU_ClkIsReset(uint32_t clk);
138 HAL_Status HAL_CRU_ClkResetAssert(uint32_t clk);
139 HAL_Status HAL_CRU_ClkResetDeassert(uint32_t clk);
/bsp/allwinner/libraries/sunxi-hal/hal/source/disp2/disp/
A Ddisp_sys_intf.h110 s32 disp_sys_clk_set_parent(hal_clk_id_t clk, hal_clk_id_t parent);
111 hal_clk_id_t disp_sys_clk_get_parent(hal_clk_id_t clk);
112 s32 disp_sys_clk_enable(hal_clk_id_t clk);
113 s32 disp_sys_clk_disable(hal_clk_id_t clk);
114 bool disp_clock_is_enabled(hal_clk_id_t clk);

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