Searched refs:clk_core (Results 1 – 11 of 11) sorted by relevance
| /bsp/allwinner/libraries/sunxi-hal/hal/source/ccmu/sunxi-ng/ |
| A D | ccu.c | 78 static struct clk_core *clk_core_get_by_pindex(struct clk_core *core, u8 p_index) in clk_core_get_by_pindex()
114 static struct clk_core *clk_core_get_parent_by_index(struct clk_core *core, in clk_core_get_parent_by_index()
132 struct clk_core *parent; in clk_hw_get_parent_by_index()
220 struct clk_core *parent; in clk_core_init_rate_req()
429 static struct clk_core *__clk_init_parent(struct clk_core *core) in __clk_init_parent()
608 struct clk_core *core; in clk_hw_register()
676 struct clk_core *core; in clk_hw_unregister()
821 u32 clk_core_recalc_rate(struct clk_core *core, struct clk_core *p_core) in clk_core_recalc_rate()
897 static int __clk_set_parent(struct clk_core *core, struct clk_core *parent, in __clk_set_parent()
967 struct clk_core *clk_core_get_parent(struct clk_core *core) in clk_core_get_parent()
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| A D | ccu.h | 44 struct clk_core;
96 struct clk_core *core;
102 struct clk_core struct
108 struct clk_core *parent; argument
123 struct clk_core *core; argument
370 struct clk_core *core;
819 struct clk_core *clk_core_get_parent(struct clk_core *core);
821 hal_clk_status_t clk_core_set_parent(struct clk_core *core, struct clk_core *parent);
823 u32 clk_core_get_rate(struct clk_core *core);
825 hal_clk_status_t clk_core_set_rate(struct clk_core *core, struct clk_core *p_core, unsigned long ra…
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| A D | clk.c | 22 struct clk_core *core = NULL; in clk_get()
83 struct clk_core *parent; in clk_get_parent()
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| /bsp/allwinner/libraries/sunxi-hal/hal/source/ccmu/sunxi/ |
| A D | clk.c | 181 periph_clk->clk_core.parent_rate = 0; in sunxi_clk_set_parent()
238 periph_clk->clk_core.current_parent = parent; in sunxi_clk_get_parent()
452 parent_rate = periph_clk->clk_core.parent_rate; in sunxi_clk_round_rate()
573 if (periph_clk->clk_core.clk_rate == rate) in sunxi_clk_set_rate()
577 parent_rate = periph_clk->clk_core.parent_rate; in sunxi_clk_set_rate()
581 periph_clk->clk_core.clk_rate = rate; in sunxi_clk_set_rate()
590 factor_clk->clk_core.clk_rate = rate; in sunxi_clk_set_rate()
633 fixed_factor->clk_core.parent_rate = parent_rate; in sunxi_fixed_factor_clk_init()
686 pclk->clk_core.current_parent = clk_init->parent; in sunxi_periph_bus_clk_init()
687 pclk->clk_core.parent_rate = parent_rate; in sunxi_periph_bus_clk_init()
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| A D | clk.h | 48 typedef struct clk_core struct
61 clk_core_t clk_core; argument
68 clk_core_t clk_core; member
74 clk_core_t clk_core; member
122 .clk_core = { \
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| A D | clk_factors.c | 292 parent_rate = clk->clk_core.parent_rate; in sunxi_clk_factors_recalc_rate()
384 parent_rate = clk->clk_core.parent_rate; in sunxi_clk_factors_set_rate()
399 … CCMU_ERR("clk %d set rate failed! Because cannot get right factors for clk\n", clk->clk_core.clk); in sunxi_clk_factors_set_rate()
460 CCMU_ERR("clk %d wait lock timeout\n", clk->clk_core.clk); in sunxi_clk_factors_set_rate()
504 parent_rate = clk->clk_core.parent_rate; in sunxi_clk_factors_round_rate()
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| A D | clk_periph.h | 73 .clk_core = { \
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| A D | clk_periph.c | 377 parent_rate = clk->clk_core.parent_rate; in sunxi_clk_periph_recalc_rate()
491 parent_rate = clk->clk_core.parent_rate; in sunxi_clk_periph_set_rate()
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| A D | clk_factors.h | 111 .clk_core = { \
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| /bsp/allwinner/libraries/sunxi-hal/hal/source/ccmu/sunxi/sun8iw19p1/ |
| A D | clk_sun8iw19.c | 1274 CCMU_DBG("clk %d current rate %d \n", factor->clk_core.clk, current_rate); in sunxi_factor_pll_cpu_init()
1275 if (factor->clk_core.clk_rate == current_rate) in sunxi_factor_pll_cpu_init()
1281 ret = sunxi_clk_factors_set_rate(factor, factor->clk_core.clk_rate); in sunxi_factor_pll_cpu_init()
1291 CCMU_DBG("clk %d recalc current rate %d \n", factor->clk_core.clk, current_rate); in sunxi_factor_pll_cpu_init()
1292 if (factor->clk_core.clk_rate != current_rate) in sunxi_factor_pll_cpu_init()
1318 factor->clk_core.clk_enbale = HAL_CLK_STATUS_ENABLED; in sunxi_factor_pll_periph1_init()
1338 factor->clk_core.clk_enbale = HAL_CLK_STATUS_ENABLED; in sunxi_factor_pll_periph0_init()
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| /bsp/allwinner/libraries/sunxi-hal/hal/source/ccmu/sunxi/sun8iw18p1/ |
| A D | clk_sun8iw18.c | 979 CCMU_DBG("clk %d current rate %d \n", factor->clk_core.clk, current_rate); in sunxi_factor_pll_cpu_init()
980 if (factor->clk_core.clk_rate == current_rate) in sunxi_factor_pll_cpu_init()
986 ret = sunxi_clk_factors_set_rate(factor, factor->clk_core.clk_rate); in sunxi_factor_pll_cpu_init()
996 CCMU_DBG("clk %d recalc current rate %d \n", factor->clk_core.clk, current_rate); in sunxi_factor_pll_cpu_init()
997 if (factor->clk_core.clk_rate != current_rate) in sunxi_factor_pll_cpu_init()
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