Searched refs:clk_src_pll3_clk0 (Results 1 – 6 of 6) sorted by relevance
| /bsp/hpmicro/hpm6750evkmini/board/ |
| A D | board.c | 864 …clock_set_source_divider(clock_aud0, clk_src_pll3_clk0, 54); /* config clock_aud1 for 22050*n samp… in board_config_i2s_clock()
866 …clock_set_source_divider(clock_aud0, clk_src_pll3_clk0, 25); /* config clock_aud0 for 8000*n sampl… in board_config_i2s_clock()
873 …clock_set_source_divider(clock_aud1, clk_src_pll3_clk0, 54); /* config clock_aud1 for 22050*n samp… in board_config_i2s_clock()
875 …clock_set_source_divider(clock_aud1, clk_src_pll3_clk0, 25); /* config clock_aud0 for 8000*n sampl… in board_config_i2s_clock()
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| /bsp/hpmicro/hpm6750evk2/board/ |
| A D | board.c | 823 …clock_set_source_divider(clock_aud0, clk_src_pll3_clk0, 54); /* config clock_aud1 for 22050*n samp… in board_config_i2s_clock()
825 …clock_set_source_divider(clock_aud0, clk_src_pll3_clk0, 25); /* config clock_aud0 for 8000*n sampl… in board_config_i2s_clock()
832 …clock_set_source_divider(clock_aud1, clk_src_pll3_clk0, 54); /* config clock_aud1 for 22050*n samp… in board_config_i2s_clock()
834 …clock_set_source_divider(clock_aud1, clk_src_pll3_clk0, 25); /* config clock_aud0 for 8000*n sampl… in board_config_i2s_clock()
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| /bsp/hpmicro/hpm6750evk/board/ |
| A D | board.c | 852 …clock_set_source_divider(clock_aud0, clk_src_pll3_clk0, 54); /* config clock_aud1 for 22050*n samp… in board_config_i2s_clock()
854 …clock_set_source_divider(clock_aud0, clk_src_pll3_clk0, 25); /* config clock_aud0 for 8000*n sampl… in board_config_i2s_clock()
861 …clock_set_source_divider(clock_aud1, clk_src_pll3_clk0, 54); /* config clock_aud1 for 22050*n samp… in board_config_i2s_clock()
863 …clock_set_source_divider(clock_aud1, clk_src_pll3_clk0, 25); /* config clock_aud0 for 8000*n sampl… in board_config_i2s_clock()
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| /bsp/hpmicro/hpm6800evk/board/ |
| A D | board.c | 1294 clock_set_source_divider(clock_aud0, clk_src_pll3_clk0, 21); /* default 24576000Hz */ in board_config_i2s_clock()
1305 clock_set_source_divider(clock_aud1, clk_src_pll3_clk0, 21); /* default 24576000Hz */ in board_config_i2s_clock()
1316 clock_set_source_divider(clock_aud3, clk_src_pll3_clk0, 21); /* default 24576000Hz */ in board_config_i2s_clock()
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| /bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/ |
| A D | hpm_clock_drv.h | 75 clk_src_pll3_clk0 = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 6), enumerator
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| /bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/ |
| A D | hpm_clock_drv.h | 66 clk_src_pll3_clk0 = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 6), enumerator
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