Searched refs:clock_out_divider (Results 1 – 2 of 2) sorted by relevance
168 reg1.clock_out_divider); in __fll_init()200 reg1.clock_out_divider = div; in __rt_fll_set_freq()
106 unsigned int clock_out_divider:4; /* Fll clock output divider, reset: 0x1 e.g div 2 */ member
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