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Searched refs:clock_out_divider (Results 1 – 2 of 2) sorted by relevance

/bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/source/
A Dhal_fll.c168 reg1.clock_out_divider); in __fll_init()
200 reg1.clock_out_divider = div; in __rt_fll_set_freq()
/bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/include/
A Dhal_fll.h106 unsigned int clock_out_divider:4; /* Fll clock output divider, reset: 0x1 e.g div 2 */ member

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