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Searched refs:clock_source (Results 1 – 25 of 64) sorted by relevance

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/bsp/hc32/ev_hc32f4a8_lqfp176/board/config/
A Dtimer_config.h25 .clock_source = CLK_BUS_PCLK0, \
44 .clock_source = CLK_BUS_PCLK0, \
63 .clock_source = CLK_BUS_PCLK0, \
82 .clock_source = CLK_BUS_PCLK0, \
101 .clock_source = CLK_BUS_PCLK1, \
120 .clock_source = CLK_BUS_PCLK1, \
139 .clock_source = CLK_BUS_PCLK1, \
158 .clock_source = CLK_BUS_PCLK1, \
177 .clock_source = CLK_BUS_PCLK1, \
196 .clock_source = CLK_BUS_PCLK1, \
[all …]
/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/
A Dtimer_config.h25 .clock_source = CLK_BUS_PCLK0, \
44 .clock_source = CLK_BUS_PCLK0, \
63 .clock_source = CLK_BUS_PCLK0, \
82 .clock_source = CLK_BUS_PCLK0, \
101 .clock_source = CLK_BUS_PCLK1, \
120 .clock_source = CLK_BUS_PCLK1, \
139 .clock_source = CLK_BUS_PCLK1, \
158 .clock_source = CLK_BUS_PCLK1, \
177 .clock_source = CLK_BUS_PCLK1, \
196 .clock_source = CLK_BUS_PCLK1, \
[all …]
/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/
A Dtimer_config.h25 .clock_source = CLK_BUS_PCLK0, \
44 .clock_source = CLK_BUS_PCLK0, \
63 .clock_source = CLK_BUS_PCLK0, \
82 .clock_source = CLK_BUS_PCLK0, \
101 .clock_source = CLK_BUS_PCLK1, \
120 .clock_source = CLK_BUS_PCLK1, \
139 .clock_source = CLK_BUS_PCLK1, \
158 .clock_source = CLK_BUS_PCLK1, \
177 .clock_source = CLK_BUS_PCLK1, \
196 .clock_source = CLK_BUS_PCLK1, \
[all …]
/bsp/hc32/ev_hc32f460_lqfp100_v2/board/config/
A Dtimer_config.h25 .clock_source = CLK_BUS_PCLK1, \
44 .clock_source = CLK_BUS_PCLK1, \
63 .clock_source = CLK_BUS_PCLK1, \
82 .clock_source = CLK_BUS_PCLK1, \
101 .clock_source = CLK_BUS_PCLK1, \
120 .clock_source = CLK_BUS_PCLK1, \
/bsp/hc32/ev_hc32f472_lqfp100/board/config/
A Dtimer_config.h26 .clock_source = CLK_BUS_PCLK0, \
45 .clock_source = CLK_BUS_PCLK0, \
64 .clock_source = CLK_BUS_PCLK0, \
83 .clock_source = CLK_BUS_PCLK0, \
102 .clock_source = CLK_BUS_PCLK1, \
121 .clock_source = CLK_BUS_PCLK1, \
/bsp/hc32/ev_hc32f334_lqfp64/board/config/
A Dtimer_config.h25 .clock_source = CLK_BUS_PCLK0, \
44 .clock_source = CLK_BUS_PCLK0, \
63 .clock_source = CLK_BUS_PCLK0, \
82 .clock_source = CLK_BUS_PCLK0, \
101 .clock_source = CLK_BUS_PCLK1, \
/bsp/hc32/ev_hc32f448_lqfp80/board/config/
A Dtimer_config.h26 .clock_source = CLK_BUS_PCLK0, \
45 .clock_source = CLK_BUS_PCLK0, \
64 .clock_source = CLK_BUS_PCLK0, \
83 .clock_source = CLK_BUS_PCLK0, \
102 .clock_source = CLK_BUS_PCLK1, \
/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/clock/clock_samd20/
A Dclock.c142 const enum system_clock_source clock_source) in system_clock_source_get_hz() argument
144 switch (clock_source) { in system_clock_source_get_hz()
441 const enum system_clock_source clock_source, in system_clock_source_write_calibration() argument
445 switch (clock_source) { in system_clock_source_write_calibration()
497 const enum system_clock_source clock_source) in system_clock_source_enable() argument
499 switch (clock_source) { in system_clock_source_enable()
545 const enum system_clock_source clock_source) in system_clock_source_disable() argument
547 switch (clock_source) { in system_clock_source_disable()
594 const enum system_clock_source clock_source) in system_clock_source_is_ready() argument
598 switch (clock_source) { in system_clock_source_is_ready()
/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/
A Dclock.c178 const enum system_clock_source clock_source) in system_clock_source_get_hz() argument
180 switch (clock_source) { in system_clock_source_get_hz()
488 const enum system_clock_source clock_source, in system_clock_source_write_calibration() argument
492 switch (clock_source) { in system_clock_source_write_calibration()
544 const enum system_clock_source clock_source) in system_clock_source_enable() argument
546 switch (clock_source) { in system_clock_source_enable()
598 const enum system_clock_source clock_source) in system_clock_source_disable() argument
600 switch (clock_source) { in system_clock_source_disable()
653 const enum system_clock_source clock_source) in system_clock_source_is_ready() argument
657 switch (clock_source) { in system_clock_source_is_ready()
/bsp/samd21/sam_d2x_asflib/sam0/drivers/ccl/
A Dccl.h216 enum gclk_generator clock_source; member
281 config->clock_source = GCLK_GENERATOR_0; in ccl_get_config_defaults()
/bsp/samd21/sam_d2x_asflib/sam0/drivers/wdt/
A Dwdt.h259 enum gclk_generator clock_source; member
331 config->clock_source = GCLK_GENERATOR_4; in wdt_is_syncing()
/bsp/bouffalo_lab/libraries/rt_drivers/
A Ddrv_wdt.c25 wdg_cfg.clock_source = BFLB_SYSTEM_XCLK; in _wdt_configure()
47 wdg_cfg.clock_source = BFLB_SYSTEM_XCLK; in _wdt_control()
/bsp/renesas/rzn2l_etherkit/rzn_gen/
A Dhal_data.c45 .clock_source = SCI_UART_CLOCK_SOURCE_SCI0ASYNCCLK,
47 .clock_source = SCI_UART_CLOCK_SOURCE_PCLKM,
/bsp/renesas/rzn2l_rsk/rzn_gen/
A Dhal_data.c45 .clock_source = SCI_UART_CLOCK_SOURCE_SCI0ASYNCCLK,
47 .clock_source = SCI_UART_CLOCK_SOURCE_PCLKM,
/bsp/renesas/rzt2m_rsk/rzt_gen/
A Dhal_data.c45 .clock_source = SCI_UART_CLOCK_SOURCE_SCI0ASYNCCLK,
47 .clock_source = SCI_UART_CLOCK_SOURCE_PCLKM,
/bsp/ti/c28x/libraries/tms320f28379d/common/source/
A DF2837xD_SysCtrl.c516 void InitSysPll(Uint16 clock_source, Uint16 imult, Uint16 fmult, Uint16 divsel) in InitSysPll() argument
524 if((clock_source == ClkCfgRegs.CLKSRCCTL1.bit.OSCCLKSRCSEL) && in InitSysPll()
535 if(clock_source != ClkCfgRegs.CLKSRCCTL1.bit.OSCCLKSRCSEL) in InitSysPll()
537 switch (clock_source) in InitSysPll()
763 switch(clock_source) in InitSysPll()
897 void InitAuxPll(Uint16 clock_source, Uint16 imult, Uint16 fmult, Uint16 divsel) in InitAuxPll() argument
905 if((clock_source == ClkCfgRegs.CLKSRCCTL2.bit.AUXOSCCLKSRCSEL) && in InitAuxPll()
916 switch (clock_source) in InitAuxPll()
/bsp/renesas/rzn2l_rsk/rzn/fsp/inc/instances/
A Dr_sci_uart.h210 sci_uart_clock_source_t clock_source; member
231 sci_uart_clock_source_t clock_source,
/bsp/renesas/rzt2m_rsk/rzt/fsp/inc/instances/
A Dr_sci_uart.h210 sci_uart_clock_source_t clock_source; member
231 sci_uart_clock_source_t clock_source,
/bsp/renesas/rzn2l_etherkit/rzn/fsp/inc/instances/
A Dr_sci_uart.h210 sci_uart_clock_source_t clock_source; member
231 sci_uart_clock_source_t clock_source,
/bsp/hc32/libraries/hc32_drivers/
A Ddrv_hwtimer.c68 rt_uint32_t clock_source; member
392 …_info[i].maxcnt = CLK_GetBusClockFreq(hc32_hwtimer_obj[i].clock_source) / 32U / 1000U; /* Period … in tmra_get_info_callback()
393 _info[i].maxfreq = CLK_GetBusClockFreq(hc32_hwtimer_obj[i].clock_source) / 32U; in tmra_get_info_callback()
394 … _info[i].minfreq = CLK_GetBusClockFreq(hc32_hwtimer_obj[i].clock_source) / 32U / _info[i].maxcnt; in tmra_get_info_callback()
/bsp/samd21/sam_d2x_asflib/sam0/drivers/tsens/
A Dtsens.c68 gclk_chan_conf.source_generator = config->clock_source; in _tsens_set_config()
187 config->clock_source = GCLK_GENERATOR_0; in tsens_get_config_defaults()
/bsp/samd21/sam_d2x_asflib/sam0/drivers/i2c/
A Di2c_slave.c72 config->clock_source = I2C_CLK_INPUT_3; in i2c_slave_get_config_defaults()
110 i2c_module->CLOCK_SOURCE_SELECT.reg = config->clock_source; in _i2c_slave_set_config()
/bsp/stm32/stm32f207-st-nucleo/.settings/
A Dprojcfg.ini7 clock_source= key
/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/
A Dbflb_wdg.h43 uint8_t clock_source; member
/bsp/samd21/sam_d2x_asflib/sam0/drivers/dualtimer/
A Ddualtimer.c80 config->clock_source = DUALTIMER_CLK_INPUT_0; in dualtimer_get_config_defaults()
246 LPMCU_MISC_REGS0->LPMCU_CTRL.bit.DUALTIMER0_CLK_SEL = config->clock_source; in dualtimer_init()

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