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Searched refs:clock_source_pll4_clk0 (Results 1 – 5 of 5) sorted by relevance

/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/
A Dhpm_clock_drv.c154 case clock_source_pll4_clk0: in get_frequency_for_source()
A Dhpm_sysctl_drv.h376 clock_source_pll4_clk0 = 7, enumerator
/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/
A Dhpm_clock_drv.c173 case clock_source_pll4_clk0: in get_frequency_for_source()
A Dhpm_sysctl_drv.h386 clock_source_pll4_clk0 = 7, enumerator
/bsp/hpmicro/hpm6750evk/board/
A Dboard.c784 clock_set_source_divider(clock_display, (clk_src_t) clock_source_pll4_clk0, 10U); in board_init_lcd_clock()

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