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Searched refs:cmd_cfg (Results 1 – 7 of 7) sorted by relevance

/bsp/nxp/mcx/mcxa/Libraries/drivers/
A Ddrv_adc.c75 lpadc_conv_command_config_t cmd_cfg; in a153_adc_enabled() local
76 LPADC_GetDefaultConvCommandConfig(&cmd_cfg); in a153_adc_enabled()
78 cmd_cfg.channelNumber = channel; in a153_adc_enabled()
79 cmd_cfg.conversionResolutionMode = kLPADC_ConversionResolutionHigh; in a153_adc_enabled()
80 cmd_cfg.hardwareAverageMode = DEFAULT_HW_AVG; in a153_adc_enabled()
81 cmd_cfg.loopCount = 0; in a153_adc_enabled()
82 cmd_cfg.sampleTimeMode = DEFAULT_SAMPLE_TIME; in a153_adc_enabled()
83 cmd_cfg.sampleChannelMode = kLPADC_SampleChannelSingleEndSideA; in a153_adc_enabled()
84 LPADC_SetConvCommandConfig(adc->adc_base, adc_chl2cmd[channel], &cmd_cfg); in a153_adc_enabled()
86 lpadc_conversion_resolution_mode_t resolution_mode = cmd_cfg.conversionResolutionMode; in a153_adc_enabled()
/bsp/nxp/mcx/mcxn/Libraries/drivers/
A Ddrv_adc.c56 lpadc_conv_command_config_t cmd_cfg; in at32_adc_enabled() local
57 LPADC_GetDefaultConvCommandConfig(&cmd_cfg); in at32_adc_enabled()
59 cmd_cfg.channelNumber = channel; in at32_adc_enabled()
60 cmd_cfg.conversionResolutionMode = kLPADC_ConversionResolutionHigh; in at32_adc_enabled()
61 cmd_cfg.hardwareAverageMode = DEFAULT_HW_AVG; in at32_adc_enabled()
62 cmd_cfg.loopCount = 0; in at32_adc_enabled()
63 cmd_cfg.sampleTimeMode = DEFAULT_SAMPLE_TIME; in at32_adc_enabled()
70 cmd_cfg.sampleChannelMode = kLPADC_SampleChannelSingleEndSideA; in at32_adc_enabled()
71 LPADC_SetConvCommandConfig(adc->adc_base, adc_chl2cmd[channel], &cmd_cfg); in at32_adc_enabled()
/bsp/hpmicro/libraries/hpm_sdk/drivers/src/
A Dhpm_mtg_drv.c298 assert((tra_index < 2) && (cmd_cfg->index < 4)); in mtg_setup_link_cfg()
299 switch (cmd_cfg->index) { in mtg_setup_link_cfg()
318 base->TRA[tra_index].CMD[cmd_cfg->index].JER_PRESET = cmd_cfg->jer_preset; in mtg_setup_link_cfg()
319 base->TRA[tra_index].CMD[cmd_cfg->index].ACC_PRESET = cmd_cfg->acc_preset; in mtg_setup_link_cfg()
320 base->TRA[tra_index].CMD[cmd_cfg->index].VEL_PRESET = cmd_cfg->vel_preset; in mtg_setup_link_cfg()
321 base->TRA[tra_index].CMD[cmd_cfg->index].POS_PRESET = cmd_cfg->pos_preset; in mtg_setup_link_cfg()
322 base->TRA[tra_index].CMD[cmd_cfg->index].REV_PRESET = cmd_cfg->rev_preset; in mtg_setup_link_cfg()
323 base->TRA[tra_index].CMD[cmd_cfg->index].CONTROL &= ~MTG_TRA_CMD_CONTROL_MODE_MASK; in mtg_setup_link_cfg()
324 base->TRA[tra_index].CMD[cmd_cfg->index].CONTROL &= ~MTG_TRA_CMD_CONTROL_OBJECT_MASK; in mtg_setup_link_cfg()
325 …base->TRA[tra_index].CMD[cmd_cfg->index].CONTROL |= MTG_TRA_CMD_CONTROL_OBJECT_SET(cmd_cfg->object… in mtg_setup_link_cfg()
[all …]
A Dhpm_enet_drv.c911 hpm_stat_t enet_set_ppsx_config(ENET_Type *ptr, enet_pps_cmd_config_t *cmd_cfg, enet_pps_idx_t idx) in enet_set_ppsx_config() argument
919 ptr->PPS0_INTERVAL = cmd_cfg->pps_interval - 1; in enet_set_ppsx_config()
920 ptr->PPS0_WIDTH = cmd_cfg->pps_width - 1; in enet_set_ppsx_config()
922 ptr->PPS[idx].INTERVAL = cmd_cfg->pps_interval - 1; in enet_set_ppsx_config()
923 ptr->PPS[idx].WIDTH = cmd_cfg->pps_width - 1; in enet_set_ppsx_config()
928 ptr->TGTTM_SEC = cmd_cfg->target_sec; in enet_set_ppsx_config()
929 ptr->TGTTM_NSEC = cmd_cfg->target_nsec; in enet_set_ppsx_config()
931 ptr->PPS[idx].TGTTM_SEC = cmd_cfg->target_sec; in enet_set_ppsx_config()
932 ptr->PPS[idx].TGTTM_NSEC = cmd_cfg->target_nsec; in enet_set_ppsx_config()
/bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/include/
A Dhal_udma_qspi_reg_defs.h124 __IO uint32_t cmd_cfg; member
/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/
A Dhpm_mtg_drv.h659 …p_link_cfg(MTG_Type *base, uint8_t tra_index, mtg_link_cfg_t link_cfg, mtg_tra_cmd_cfg_t *cmd_cfg);
A Dhpm_enet_drv.h844 hpm_stat_t enet_set_ppsx_config(ENET_Type *ptr, enet_pps_cmd_config_t *cmd_cfg, enet_pps_idx_t idx);

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