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/bsp/allwinner/libraries/sunxi-hal/hal/source/ccmu/sunxi-ng/
A Dccu-sun8iw20.c38 .common = {
55 .common = {
71 .common = {
99 .common = {
118 .common = {
135 .common = {
167 .common = {
191 .common = {
844 &di_clk.common,
848 &ce_clk.common,
[all …]
A Dccu_frac.c13 if (!(common->features & CCU_FEATURE_FRACTIONAL)) in ccu_frac_helper_is_enabled()
18 return !(readl(common->base + common->reg) & cf->enable); in ccu_frac_helper_is_enabled()
32 __cspr = hal_spin_lock_irqsave(&common->lock); in ccu_frac_helper_enable()
33 reg = readl(common->base + common->reg); in ccu_frac_helper_enable()
34 writel(reg & ~cf->enable, common->base + common->reg); in ccu_frac_helper_enable()
50 reg = readl(common->base + common->reg); in ccu_frac_helper_disable()
51 writel(reg | cf->enable, common->base + common->reg); in ccu_frac_helper_disable()
82 reg = readl(common->base + common->reg); in ccu_frac_helper_read_rate()
116 reg = readl(common->base + common->reg); in ccu_frac_helper_set_rate()
118 writel(reg | sel, common->base + common->reg); in ccu_frac_helper_set_rate()
[all …]
A Dccu_sdm.c18 if (sdm->enable && !(readl(common->base + common->reg) & sdm->enable)) in ccu_sdm_helper_is_enabled()
26 void ccu_sdm_helper_enable(struct ccu_common *common, in ccu_sdm_helper_enable() argument
43 common->base + sdm->tuning_reg); in ccu_sdm_helper_enable()
46 __cspr = hal_spin_lock_irqsave(&common->lock); in ccu_sdm_helper_enable()
47 reg = readl(common->base + sdm->tuning_reg); in ccu_sdm_helper_enable()
51 __cspr = hal_spin_lock_irqsave(&common->lock); in ccu_sdm_helper_enable()
52 reg = readl(common->base + common->reg); in ccu_sdm_helper_enable()
53 writel(reg | sdm->enable, common->base + common->reg); in ccu_sdm_helper_enable()
69 reg = readl(common->base + common->reg); in ccu_sdm_helper_disable()
70 writel(reg & ~sdm->enable, common->base + common->reg); in ccu_sdm_helper_disable()
[all …]
A Dccu_gate.c19 __cspr = hal_spin_lock_irqsave(&common->lock); in ccu_gate_helper_disable()
21 reg = readl(common->base + common->reg); in ccu_gate_helper_disable()
22 writel(reg & ~gate, common->base + common->reg); in ccu_gate_helper_disable()
24 hal_spin_unlock_irqrestore(&common->lock, __cspr); in ccu_gate_helper_disable()
44 __cspr = hal_spin_lock_irqsave(&common->lock); in ccu_gate_helper_enable()
46 reg = readl(common->base + common->reg); in ccu_gate_helper_enable()
47 writel(reg | gate, common->base + common->reg); in ccu_gate_helper_enable()
49 hal_spin_unlock_irqrestore(&common->lock, __cspr); in ccu_gate_helper_enable()
70 value = readl(common->base + common->reg); in ccu_gate_helper_is_enabled()
89 rate /= cg->common.prediv; in ccu_gate_recalc_rate()
[all …]
A Dccu_mux.c10 static u16 ccu_mux_get_prediv(struct ccu_common *common, in ccu_mux_get_prediv() argument
19 (common->features & CCU_FEATURE_ALL_PREDIV))) in ccu_mux_get_prediv()
24 if (common->features & CCU_FEATURE_ALL_PREDIV) in ccu_mux_get_prediv()
26 return common->prediv; in ccu_mux_get_prediv()
29 reg = readl(common->base + common->reg); in ccu_mux_get_prediv()
36 if (common->features & CCU_FEATURE_FIXED_PREDIV) in ccu_mux_get_prediv()
92 struct clk_hw *best_parent, *hw = &common->hw; in ccu_mux_helper_determine_rate()
175 reg = readl(common->base + common->reg); in ccu_mux_helper_get_parent()
206 __cspr = hal_spin_lock_irqsave(&common->lock); in ccu_mux_helper_set_parent()
208 reg = readl(common->base + common->reg); in ccu_mux_helper_set_parent()
[all …]
A Dccu-sun8iw20-r.c63 &r_ahb_clk.common,
64 &r_apb0_clk.common,
65 &r_apb0_timer_clk.common,
66 &r_apb0_twd_clk.common,
67 &r_ppu_clk.common,
68 &r_apb0_ir_rx_clk.common,
69 &r_apb0_bus_ir_rx_clk.common,
70 &r_ahb_bus_rtc_clk.common,
71 &r_apb0_cpucfg_clk.common,
77 [CLK_R_AHB] = &r_ahb_clk.common.hw,
[all …]
A Dccu_nm.c101 reg = readl(nm->common.base + nm->common.reg); in ccu_nm_recalc_rate()
128 if (nm->common.features & CCU_FEATURE_FIXED_POSTDIV) in ccu_nm_recalc_rate()
142 if (nm->common.features & CCU_FEATURE_FIXED_POSTDIV) in ccu_nm_round_rate()
220 reg = readl(nm->common.base + nm->common.reg); in ccu_nm_set_rate()
222 writel(reg, nm->common.base + nm->common.reg); in ccu_nm_set_rate()
226 ccu_frac_helper_enable(&nm->common, &nm->frac); in ccu_nm_set_rate()
251 ccu_sdm_helper_disable(&nm->common, &nm->sdm); in ccu_nm_set_rate()
255 __cspr = hal_spin_lock_irqsave(&nm->common.lock); in ccu_nm_set_rate()
257 reg = readl(nm->common.base + nm->common.reg); in ccu_nm_set_rate()
263 writel(reg, nm->common.base + nm->common.reg); in ccu_nm_set_rate()
[all …]
A Dccu_mult.c63 return ccu_gate_helper_disable(&cm->common, cm->enable); in ccu_mult_disable()
70 return ccu_gate_helper_enable(&cm->common, cm->enable); in ccu_mult_enable()
87 if (ccu_frac_helper_is_enabled(&cm->common, &cm->frac)) in ccu_mult_recalc_rate()
92 reg = readl(cm->common.base + cm->common.reg); in ccu_mult_recalc_rate()
121 ccu_frac_helper_enable(&cm->common, &cm->frac); in ccu_mult_set_rate()
128 ccu_frac_helper_disable(&cm->common, &cm->frac); in ccu_mult_set_rate()
147 __cspr = hal_spin_lock_irqsave(&cm->common.lock); in ccu_mult_set_rate()
149 reg = readl(cm->common.base + cm->common.reg); in ccu_mult_set_rate()
153 writel(reg, cm->common.base + cm->common.reg); in ccu_mult_set_rate()
155 hal_spin_unlock_irqrestore(&cm->common.lock, __cspr); in ccu_mult_set_rate()
[all …]
A Dccu-sun8iw20-rtc.c68 &iosc_clk.common,
69 &ext32k_gate_clk.common,
70 &osc32k_clk.common,
71 &dcxo24M_div32k_clk.common,
72 &rtc32k_clk.common,
73 &rtc_32k_fanout_clk.common,
74 &rtc_spi_clk.common,
80 [CLK_IOSC] = &iosc_clk.common.hw,
83 [CLK_OSC32K] = &osc32k_clk.common.hw,
85 [CLK_RTC32K] = &rtc32k_clk.common.hw,
[all …]
A Dccu_div.c18 if (cd->common.features & CCU_FEATURE_FIXED_POSTDIV) in ccu_div_round_rate()
23 rate = divider_round_rate_parent(&cd->common.hw, parent, in ccu_div_round_rate()
28 if (cd->common.features & CCU_FEATURE_FIXED_POSTDIV) in ccu_div_round_rate()
47 return ccu_gate_helper_enable(&cd->common, cd->enable); in ccu_div_enable()
64 reg = readl(cd->common.base + cd->common.reg); in ccu_div_recalc_rate()
74 if (cd->common.features & CCU_FEATURE_FIXED_POSTDIV) in ccu_div_recalc_rate()
102 if (cd->common.features & CCU_FEATURE_FIXED_POSTDIV) in ccu_div_set_rate()
110 __cspr = hal_spin_lock_irqsave(&cd->common.lock); in ccu_div_set_rate()
112 reg = readl(cd->common.base + cd->common.reg); in ccu_div_set_rate()
116 cd->common.base + cd->common.reg); in ccu_div_set_rate()
[all …]
A Dccu_gate.h17 struct ccu_common common; member
25 .common = { \
39 .common = { \
54 .common = { \
68 .common = { \
80 .common = { \
92 .common = { \
108 .common = { \
120 .common = { \
132 struct ccu_common *common = hw_to_ccu_common(hw); in hw_to_ccu_gate() local
[all …]
A Dccu_nk.c52 return ccu_gate_helper_disable(&nk->common, nk->enable); in ccu_nk_disable()
59 return ccu_gate_helper_enable(&nk->common, nk->enable); in ccu_nk_enable()
76 reg = readl(nk->common.base + nk->common.reg); in ccu_nk_recalc_rate()
95 if (nk->common.features & CCU_FEATURE_FIXED_POSTDIV) in ccu_nk_recalc_rate()
109 if (nk->common.features & CCU_FEATURE_FIXED_POSTDIV) in ccu_nk_round_rate()
122 if (nk->common.features & CCU_FEATURE_FIXED_POSTDIV) in ccu_nk_round_rate()
138 if (nk->common.features & CCU_FEATURE_FIXED_POSTDIV) in ccu_nk_set_rate()
150 __cspr = hal_spin_lock_irqsave(&nk->common.lock); in ccu_nk_set_rate()
152 reg = readl(nk->common.base + nk->common.reg); in ccu_nk_set_rate()
158 writel(reg, nk->common.base + nk->common.reg); in ccu_nk_set_rate()
[all …]
A Dccu_nkm.c65 return ccu_gate_helper_enable(&nkm->common, nkm->enable); in ccu_nkm_enable()
82 reg = readl(nkm->common.base + nkm->common.reg); in ccu_nkm_recalc_rate()
110 if (nkm->common.features & CCU_FEATURE_FIXED_POSTDIV) in ccu_nkm_recalc_rate()
134 if (nkm->common.features & CCU_FEATURE_FIXED_POSTDIV) in ccu_nkm_round_rate()
143 if (nkm->common.features & CCU_FEATURE_FIXED_POSTDIV) in ccu_nkm_round_rate()
168 if (nkm->common.features & CCU_FEATURE_FIXED_POSTDIV) in ccu_nkm_set_rate()
182 __cspr = hal_spin_lock_irqsave(&nkm->common.lock); in ccu_nkm_set_rate()
184 reg = readl(nkm->common.base + nkm->common.reg); in ccu_nkm_set_rate()
192 writel(reg, nkm->common.base + nkm->common.reg); in ccu_nkm_set_rate()
194 hal_spin_unlock_irqrestore(&nkm->common.lock, __cspr); in ccu_nkm_set_rate()
[all …]
A Dccu_mp.c135 if (cmp->common.features & CCU_FEATURE_FIXED_POSTDIV) in ccu_mp_round_rate()
154 if (cmp->common.features & CCU_FEATURE_FIXED_POSTDIV) in ccu_mp_round_rate()
166 return ccu_gate_helper_disable(&cmp->common, cmp->enable); in ccu_mp_disable()
173 return ccu_gate_helper_enable(&cmp->common, cmp->enable); in ccu_mp_enable()
195 reg = readl(cmp->common.base + cmp->common.reg); in ccu_mp_recalc_rate()
209 if (cmp->common.features & CCU_FEATURE_FIXED_POSTDIV) in ccu_mp_recalc_rate()
243 if (cmp->common.features & CCU_FEATURE_FIXED_POSTDIV) in ccu_mp_set_rate()
250 __cspr = hal_spin_lock_irqsave(&cmp->common.lock); in ccu_mp_set_rate()
252 reg = readl(cmp->common.base + cmp->common.reg); in ccu_mp_set_rate()
258 writel(reg, cmp->common.base + cmp->common.reg); in ccu_mp_set_rate()
[all …]
A Dccu_mux.h56 struct ccu_common common; member
65 .common = { \
82 .common = { \
104 struct ccu_common *common = hw_to_ccu_common(hw); in hw_to_ccu_mux() local
106 return container_of(common, struct ccu_mux, common); in hw_to_ccu_mux()
111 unsigned long ccu_mux_helper_apply_prediv(struct ccu_common *common,
115 int ccu_mux_helper_determine_rate(struct ccu_common *common,
124 u8 ccu_mux_helper_get_parent(struct ccu_common *common,
126 int ccu_mux_helper_set_parent(struct ccu_common *common,
A Dccu_frac.h27 bool ccu_frac_helper_is_enabled(struct ccu_common *common,
29 void ccu_frac_helper_enable(struct ccu_common *common,
31 void ccu_frac_helper_disable(struct ccu_common *common,
34 bool ccu_frac_helper_has_rate(struct ccu_common *common,
38 unsigned long ccu_frac_helper_read_rate(struct ccu_common *common,
41 int ccu_frac_helper_set_rate(struct ccu_common *common,
A Dccu_nkmp.c105 return ccu_gate_helper_enable(&nkmp->common, nkmp->enable); in ccu_nkmp_enable()
122 reg = readl(nkmp->common.base + nkmp->common.reg); in ccu_nkmp_recalc_rate()
152 if (nkmp->common.features & CCU_FEATURE_FIXED_POSTDIV) in ccu_nkmp_recalc_rate()
166 if (nkmp->common.features & CCU_FEATURE_FIXED_POSTDIV) in ccu_nkmp_round_rate()
194 if (nkmp->common.features & CCU_FEATURE_FIXED_POSTDIV) in ccu_nkmp_round_rate()
211 if (nkmp->common.features & CCU_FEATURE_FIXED_POSTDIV) in ccu_nkmp_set_rate()
246 __cspr = hal_spin_lock_irqsave(&nkmp->common.lock); in ccu_nkmp_set_rate()
248 reg = readl(nkmp->common.base + nkmp->common.reg); in ccu_nkmp_set_rate()
256 writel(reg, nkmp->common.base + nkmp->common.reg); in ccu_nkmp_set_rate()
258 hal_spin_unlock_irqrestore(&nkmp->common.lock, __cspr); in ccu_nkmp_set_rate()
[all …]
A Dccu_phase.c19 reg = readl(phase->common.base + phase->common.reg); in ccu_phase_get_phase()
129 __cspr = hal_spin_lock_irqsave(&phase->common.lock); in ccu_phase_set_phase()
130 reg = readl(phase->common.base + phase->common.reg); in ccu_phase_set_phase()
133 phase->common.base + phase->common.reg); in ccu_phase_set_phase()
134 hal_spin_unlock_irqrestore(&phase->common.lock, __cspr); in ccu_phase_set_phase()
A Dccu_sdm.h52 bool ccu_sdm_helper_is_enabled(struct ccu_common *common,
54 void ccu_sdm_helper_enable(struct ccu_common *common,
57 void ccu_sdm_helper_disable(struct ccu_common *common,
60 bool ccu_sdm_helper_has_rate(struct ccu_common *common,
64 unsigned long ccu_sdm_helper_read_rate(struct ccu_common *common,
68 int ccu_sdm_helper_get_factors(struct ccu_common *common,
A Dccu_phase.h17 struct ccu_common common; member
24 .common = { \
35 struct ccu_common *common = hw_to_ccu_common(hw); in hw_to_ccu_phase() local
37 return container_of(common, struct ccu_phase, common); in hw_to_ccu_phase()
A Dccu_mp.h30 struct ccu_common common; member
43 .common = { \
64 .common = { \
84 .common = { \
106 struct ccu_common *common = hw_to_ccu_common(hw); in hw_to_ccu_mp() local
108 return container_of(common, struct ccu_mp, common); in hw_to_ccu_mp()
129 .common = { \
/bsp/ck802/libraries/
A DSConscript11 common/aes/ck_aes.c
12 common/crc/ck_crc.c
13 common/dmac/ck_dmac.c
15 common/pwm/ck_pwm.c
16 common/rsa/ck_rsa.c
17 common/sha/ck_sha.c
18 common/trng/ck_trng.c
20 common/gpio/dw_gpio.c
21 common/spi/dw_spi.c
22 common/iic/dw_iic.c
[all …]
/bsp/ti/c28x/libraries/tms320f28379d/
A DSConscript10 common/source/F2837xD_PieCtrl.c
11 common/source/F2837xD_PieVect.c
12 common/source/F2837xD_SysCtrl.c
13 common/source/F2837xD_CpuTimers.c
15 common/source/F2837xD_DefaultISR.c
16 common/source/F2837xD_Gpio.c
17 common/source/F2837xD_usDelay.asm
22 src += ['common/source/F2837xD_Adc.c']
25 src += ['common/source/F2837xD_can.c']
30 src += ['common/source/F2837xD_Dma.c']
[all …]
/bsp/stm32/stm32mp157a-st-discovery/board/ports/OpenAMP/libmetal/lib/
A Dinit.c16 _metal.common.log_handler = params->log_handler; in metal_init()
17 _metal.common.log_level = params->log_level; in metal_init()
19 metal_list_init(&_metal.common.bus_list); in metal_init()
20 metal_list_init(&_metal.common.generic_shmem_list); in metal_init()
21 metal_list_init(&_metal.common.generic_device_list); in metal_init()
/bsp/stm32/stm32mp157a-st-ev1/board/ports/OpenAMP/libmetal/lib/
A Dinit.c16 _metal.common.log_handler = params->log_handler; in metal_init()
17 _metal.common.log_level = params->log_level; in metal_init()
19 metal_list_init(&_metal.common.bus_list); in metal_init()
20 metal_list_init(&_metal.common.generic_shmem_list); in metal_init()
21 metal_list_init(&_metal.common.generic_device_list); in metal_init()

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