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/bsp/bouffalo_lab/libraries/
A DKconfig3 config BSP_DRIVER_DEBUG
19 config UART0_TX_USING_GPIO0
659 config BSP_USING_GPIO
664 config BSP_USING_ADC
762 config BSP_USING_RTC
767 config BSP_USING_WDT
777 config BSP_USING_PWM0
781 config BSP_USING_PWM1
785 config BSP_USING_PWM2
789 config BSP_USING_PWM3
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/bsp/samd21/sam_d2x_asflib/sam0/drivers/opamp/
A Dopamp.c71 Assert(config); in _opamp_get_config_common_defaults()
76 config->r2_vcc = false; in _opamp_get_config_common_defaults()
77 config->r2_out = false; in _opamp_get_config_common_defaults()
87 Assert(config); in opamp0_get_config_defaults()
100 Assert(config); in opamp1_get_config_defaults()
113 Assert(config); in opamp2_get_config_defaults()
155 config->positive_input| in opamp0_set_config()
156 config->r1_connection; in opamp0_set_config()
191 config->positive_input| in opamp1_set_config()
192 config->r1_connection; in opamp1_set_config()
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/bsp/bouffalo_lab/bl808/d0/board/
A DKconfig1 config BSP_USING_BL808
14 config BL808_CORE_D0
18 config C906_PLIC_PHY_ADDR
22 config IRQ_MAX_NR
26 config TIMER_CLK_FREQ
40 config UART3_TX_USING_GPIO0
42 config UART3_TX_USING_GPIO4
44 config UART3_TX_USING_GPIO8
46 config UART3_TX_USING_GPIO12
48 config UART3_TX_USING_GPIO16
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/bsp/hpmicro/libraries/hpm_sdk/drivers/src/
A Dhpm_cam_drv.c15 config->width = 320; in cam_get_default_config()
16 config->height = 240; in cam_get_default_config()
17 config->buffer1 = -1; in cam_get_default_config()
18 config->buffer2 = -1; in cam_get_default_config()
20 config->hsync_active_low = false; in cam_get_default_config()
21 config->vsync_active_low = false; in cam_get_default_config()
23 config->de_active_low = false; in cam_get_default_config()
25 config->color_ext = false; in cam_get_default_config()
26 config->data_pack_msb = false; in cam_get_default_config()
84 width = config->width; in cam_init()
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A Dhpm_sei_drv.c23 | SEI_CTRL_XCVR_CTRL_MODE_SET(config->mode); in sei_tranceiver_config_init()
26 switch (config->mode) { in sei_tranceiver_config_init()
34 …baud_div = (config->src_clk_freq + (config->synchronous_master_config.baudrate >> 1u)) / config->s… in sei_tranceiver_config_init()
54 …baud_div = (config->src_clk_freq + (config->synchronous_slave_config.max_baudrate >> 1u)) / config… in sei_tranceiver_config_init()
60 … ck0_point = config->synchronous_slave_config.ck0_timeout_us * (config->src_clk_freq / 1000000u); in sei_tranceiver_config_init()
64 … ck1_point = config->synchronous_slave_config.ck1_timeout_us * (config->src_clk_freq / 1000000u); in sei_tranceiver_config_init()
131 word_len = config->word_len; in sei_cmd_data_format_config_init()
135 crc_len = config->crc_len; in sei_cmd_data_format_config_init()
139 tmp = SEI_DAT_MODE_MODE_SET(config->mode) in sei_cmd_data_format_config_init()
155 | SEI_DAT_IDX_MAX_BIT_SET(config->max_bit) in sei_cmd_data_format_config_init()
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A Dhpm_vsc_drv.c14 config->phase_mode = vsc_abc_phase; in vsc_get_default_config()
15 config->a_adc_config.adc_sel = vsc_sel_adc0; in vsc_get_default_config()
16 config->b_adc_config.adc_sel = vsc_sel_adc1; in vsc_get_default_config()
17 config->c_adc_config.adc_sel = vsc_sel_adc2; in vsc_get_default_config()
18 config->a_adc_config.adc_chn = 0; in vsc_get_default_config()
19 config->b_adc_config.adc_chn = 0; in vsc_get_default_config()
20 config->c_adc_config.adc_chn = 0; in vsc_get_default_config()
25 config->a_data_cnt = 1; in vsc_get_default_config()
30 config->b_data_cnt = 1; in vsc_get_default_config()
35 config->c_data_cnt = 1; in vsc_get_default_config()
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A Dhpm_qeiv2_drv.c19 …qeiv2_set_cmp_match_option(qeiv2_x, config->ignore_zcmp, false, false, config->ignore_rotate_dir, … in qeiv2_config_phcnt_cmp_match_condition()
29 …(qeiv2_x, true, true, false, true, qeiv2_rotate_dir_forward, config->ignore_pos_dir, config->pos_d… in qeiv2_config_position_cmp_match_condition()
41 …qeiv2_set_cmp2_match_option(qeiv2_x, config->ignore_zcmp, false, false, config->ignore_rotate_dir,… in qeiv2_config_phcnt_cmp2_match_condition()
57 config->pos_opt = qeiv2_uvw_pos_opt_current; in qeiv2_get_uvw_position_defconfig()
60 config->v_pos_sel[0] = qeiv2_uvw_pos_sel_low; in qeiv2_get_uvw_position_defconfig()
64 config->v_pos_sel[1] = qeiv2_uvw_pos_sel_low; in qeiv2_get_uvw_position_defconfig()
65 config->w_pos_sel[1] = qeiv2_uvw_pos_sel_low; in qeiv2_get_uvw_position_defconfig()
69 config->w_pos_sel[2] = qeiv2_uvw_pos_sel_low; in qeiv2_get_uvw_position_defconfig()
71 config->u_pos_sel[3] = qeiv2_uvw_pos_sel_low; in qeiv2_get_uvw_position_defconfig()
73 config->w_pos_sel[3] = qeiv2_uvw_pos_sel_low; in qeiv2_get_uvw_position_defconfig()
[all …]
A Dhpm_ppi_drv.c14 tmp = PPI_CLKPIN_CFG_CYCLE_SET(config->cycle_num) in ppi_config_clk_pin()
15 | PPI_CLKPIN_CFG_HIGH_SET(config->high_num) in ppi_config_clk_pin()
16 | PPI_CLKPIN_CFG_LOW_SET(config->low_num) in ppi_config_clk_pin()
17 | PPI_CLKPIN_CFG_INVERT_SET(config->revert) in ppi_config_clk_pin()
18 | PPI_CLKPIN_CFG_AON_SET(config->mode) in ppi_config_clk_pin()
30 assert((config->addr_start_high_12bits >= 0xF80) && (config->addr_start_high_12bits <= 0xFFF)); in ppi_config_cs_pin()
31 assert((config->addr_end_high_12bits >= 0xF80) && (config->addr_end_high_12bits <= 0xFFF)); in ppi_config_cs_pin()
33 …tmp = PPI_CS_CFG0_ADDR_START_SET(config->addr_start_high_12bits) | PPI_CS_CFG0_ADDR_END_SET(config… in ppi_config_cs_pin()
36 if (config->port_size == ppi_port_size_16bits) { in ppi_config_cs_pin()
46 tmp = PPI_CS_CFG3_RCMD_END1_SET(config->rcmd_end1) in ppi_config_cs_pin()
[all …]
A Dhpm_lobs_drv.c39 lobs->STARTADDR = config->start_addr; in lobs_ctrl_config()
45 assert(config->sig_group_num < 12); in lobs_two_group_mode_config()
52 … | LOBS_SIGENA_EN1_SET((config->sample_sig_en[0]) | (config->sample_sig_en[1] << 1) in lobs_two_group_mode_config()
53 … | (config->sample_sig_en[2] << 2) | (config->sample_sig_en[3] << 3)); in lobs_two_group_mode_config()
60 … | LOBS_SIGENA_EN2_SET((config->sample_sig_en[0]) | (config->sample_sig_en[1] << 1) in lobs_two_group_mode_config()
75 assert((config->cmp_sig_en[0] && (config->cmp_sig_bit[0] < 128)) || (!config->cmp_sig_en[0])); in lobs_state_config()
76 assert((config->cmp_sig_en[1] && (config->cmp_sig_bit[1] < 128)) || (!config->cmp_sig_en[1])); in lobs_state_config()
77 assert((config->cmp_sig_en[2] && (config->cmp_sig_bit[2] < 128)) || (!config->cmp_sig_en[2])); in lobs_state_config()
78 assert((config->cmp_sig_en[3] && (config->cmp_sig_bit[3] < 128)) || (!config->cmp_sig_en[3])); in lobs_state_config()
79 …assert(((config->cmp_mode == lobs_cnt_cmp_mode) && (config->state_chg_condition == lobs_cnt_matche… in lobs_state_config()
[all …]
A Dhpm_i2s_drv.c96 config->tx_fifo_threshold = 4; in i2s_get_default_config()
182 || !config->sample_rate in _i2s_config_tx()
190 ptr->TXDSLOT[config->data_line] = config->channel_slot_mask; in _i2s_config_tx()
209 || !config->sample_rate in _i2s_config_rx()
217 ptr->RXDSLOT[config->data_line] = config->channel_slot_mask; in _i2s_config_rx()
230 || !config->sample_rate in _i2s_config_transfer()
239 ptr->RXDSLOT[config->data_line] = config->channel_slot_mask; in _i2s_config_transfer()
240 ptr->TXDSLOT[config->data_line] = config->channel_slot_mask; in _i2s_config_transfer()
260 bclk_in_hz = config->sample_rate * config->channel_length * channel_num_per_frame; in i2s_config_tx()
285 bclk_in_hz = config->sample_rate * config->channel_length * channel_num_per_frame; in i2s_config_rx()
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A Dhpm_femc_drv.c86 config->cmd_timeout = 0; in femc_default_config()
229 prescaler = ((config->prescaler == 0) ? FEMC_PRESCALER_MAX : config->prescaler); in femc_config_sdram()
245 ptr->BR[config->cs] = FEMC_BR_BASE_SET(config->base_address >> FEMC_BR_BASE_SHIFT) in femc_config_sdram()
327 config->oeh_in_ns = 0; in femc_get_typical_sram_config()
328 config->oel_in_ns = 50; in femc_get_typical_sram_config()
329 config->weh_in_ns = 0; in femc_get_typical_sram_config()
330 config->wel_in_ns = 50; in femc_get_typical_sram_config()
331 config->ah_in_ns = 50; in femc_get_typical_sram_config()
332 config->as_in_ns = 0; in femc_get_typical_sram_config()
333 config->ceh_in_ns = 0; in femc_get_typical_sram_config()
[all …]
A Dhpm_qeov2_drv.c35 config->dq_valid_trig_enable = false; in qeo_wave_get_default_mode_config()
37 config->vd_vq_inject_enable = false; in qeo_wave_get_default_mode_config()
38 config->vd_vq_from_sw = false; in qeo_wave_get_default_mode_config()
40 config->saddle_type = 0; in qeo_wave_get_default_mode_config()
41 config->wave_type = qeo_wave_cosine; in qeo_wave_get_default_mode_config()
78 config->a_inv_pol = false; in qeo_abz_get_default_mode_config()
79 config->b_inv_pol = false; in qeo_abz_get_default_mode_config()
80 config->z_inv_pol = false; in qeo_abz_get_default_mode_config()
81 config->enable_wdog = false; in qeo_abz_get_default_mode_config()
82 config->sync_step_position = true; in qeo_abz_get_default_mode_config()
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A Dhpm_adc12_drv.c16 config->wait_dis = true; in adc12_get_default_config()
17 config->sel_sync_ahb = true; in adc12_get_default_config()
18 config->adc_ahb_en = false; in adc12_get_default_config()
23 config->ch = 0; in adc12_get_channel_default_config()
25 config->sample_cycle = 10; in adc12_get_channel_default_config()
26 config->sample_cycle_shift = 0; in adc12_get_channel_default_config()
27 config->thshdh = 0xfff; in adc12_get_channel_default_config()
182 ptr->PRD_CFG[config->ch].PRD_THSHD_CFG = ADC12_PRD_CFG_PRD_THSHD_CFG_THSHDH_SET(config->thshdh) in adc12_init_channel()
188 ptr->SAMPLE_CFG[config->ch] = ADC12_SAMPLE_CFG_DIFF_SEL_SET(config->diff_sel) in adc12_init_channel()
193 if (config->wdog_int_en) { in adc12_init_channel()
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A Dhpm_qeo_drv.c34 config->saddle_type = 0; in qeo_wave_get_default_mode_config()
35 config->wave_type = qeo_wave_cosine; in qeo_wave_get_default_mode_config()
72 config->a_inv_pol = false; in qeo_abz_get_default_mode_config()
73 config->b_inv_pol = false; in qeo_abz_get_default_mode_config()
74 config->z_inv_pol = false; in qeo_abz_get_default_mode_config()
75 config->output_type = qeo_abz_output_abz; in qeo_abz_get_default_mode_config()
76 config->z_pulse_period = qeo_z_pulse_100_percent; in qeo_abz_get_default_mode_config()
92 …if ((config->output_type == qeo_abz_output_pulse_revise) || (config->output_type == qeo_abz_output… in qeo_abz_config_mode()
162 config->phase_num = 4; in qeo_pwm_get_default_mode_config()
163 config->shield_hardware_trig_safety = false; in qeo_pwm_get_default_mode_config()
[all …]
A Dhpm_smix_drv.c42 config->priority = 0; in smix_get_dma_default_ch_config()
50 config->trans_bytes = 0; in smix_get_dma_default_ch_config()
51 config->linked_ptr = 0; in smix_get_dma_default_ch_config()
52 config->src_req_sel = 0; in smix_get_dma_default_ch_config()
53 config->dst_req_sel = 0; in smix_get_dma_default_ch_config()
67 config->da_int_en = false; in smix_get_mixer_dst_ch_default_config()
71 config->active_en = true; in smix_get_mixer_dst_ch_default_config()
76 config->mixer_en = true; in smix_get_mixer_dst_ch_default_config()
105 if ((config->trans_bytes & ((1 << config->dst_width) - 1)) in smix_config_dma_channel()
106 || (config->src_addr & ((1 << config->src_width) - 1)) in smix_config_dma_channel()
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/bsp/samd21/sam_d2x_asflib/common/services/adp/
A Dadp.h285 Assert(config); in adp_configure_stream_get_defaults()
344 Assert(config); in adp_configure_graph_get_defaults()
382 Assert(config); in adp_add_axis_to_graph_get_defaults()
435 Assert(config); in adp_add_stream_to_axis_get_defaults()
484 Assert(config); in adp_add_cursor_to_graph_get_defaults()
527 Assert(config); in adp_gpio_to_graph_get_defaults()
560 Assert(config); in adp_configure_terminal_get_defaults()
593 Assert(config); in adp_add_stream_to_terminal_get_defaults()
614 Assert(config); in adp_conf_dashboard_get_defaults()
674 config->x = 0; in adp_conf_dashboard_element_get_defaults()
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/bsp/hpmicro/libraries/hpm_sdk/components/adc/
A Dhpm_adc.h213 return adc12_init(config->adc_base.adc12, &config->config.adc12); in hpm_adc_init()
219 return adc16_init(config->adc_base.adc16, &config->config.adc16); in hpm_adc_init()
239 return adc12_init_channel(config->adc_base.adc12, &config->config.adc12_ch); in hpm_adc_channel_init()
245 return adc16_init_channel(config->adc_base.adc16, &config->config.adc16_ch); in hpm_adc_channel_init()
266 return adc12_set_prd_config(config->adc_base.adc12, &config->config.adc12); in hpm_adc_set_period_config()
272 return adc16_set_prd_config(config->adc_base.adc16, &config->config.adc16); in hpm_adc_set_period_config()
292 return adc12_set_seq_config(config->adc_base.adc12, &config->config.adc12); in hpm_adc_set_sequence_config()
298 return adc16_set_seq_config(config->adc_base.adc16, &config->config.adc16); in hpm_adc_set_sequence_config()
318 return adc12_set_pmt_config(config->adc_base.adc12, &config->config.adc12); in hpm_adc_set_preempt_config()
380 adc12_init_seq_dma(config->adc_base.adc12, &config->config.adc12); in hpm_adc_init_seq_dma()
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/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/
A Dald_adc.c606 config->config.ch = config->adc_ch; in ald_adc_timer_trigger_adc_by_dma()
607 config->config.idx = ADC_NCH_IDX_1; in ald_adc_timer_trigger_adc_by_dma()
608 config->config.samp = ADC_SAMPLETIME_4; in ald_adc_timer_trigger_adc_by_dma()
609 ald_adc_normal_channel_config(&config->h_adc, &config->config); in ald_adc_timer_trigger_adc_by_dma()
612 config->h_dma.cplt_arg = config; in ald_adc_timer_trigger_adc_by_dma()
614 config->h_dma.err_arg = &config->h_adc; in ald_adc_timer_trigger_adc_by_dma()
618 config->h_dma.config.src = (void *)&config->h_adc.perh->NCHDR; in ald_adc_timer_trigger_adc_by_dma()
619 config->h_dma.config.dst = (void *)config->buf; in ald_adc_timer_trigger_adc_by_dma()
620 config->h_dma.config.size = config->size; in ald_adc_timer_trigger_adc_by_dma()
626 config->h_dma.config.burst = ENABLE; in ald_adc_timer_trigger_adc_by_dma()
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/bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Source/
A Dald_adc.c479 config->i_config.ch = config->adc_ch; in ald_adc_timer_trigger_insert()
549 config->config.ch = config->adc_ch; in ald_adc_timer_trigger_adc_by_dma()
550 config->config.idx = ALD_ADC_NCH_IDX_1; in ald_adc_timer_trigger_adc_by_dma()
551 config->config.samp = ALD_ADC_SAMPLETIME_4; in ald_adc_timer_trigger_adc_by_dma()
552 ald_adc_normal_channel_config(&config->h_adc, &config->config); in ald_adc_timer_trigger_adc_by_dma()
555 config->h_dma.cplt_tc_arg = config; in ald_adc_timer_trigger_adc_by_dma()
557 ald_dma_config_struct(&config->h_dma.config); in ald_adc_timer_trigger_adc_by_dma()
559 config->h_dma.config.src = (void *)&config->h_adc.perh->NCHDR; in ald_adc_timer_trigger_adc_by_dma()
560 config->h_dma.config.dst = (void *)config->buf; in ald_adc_timer_trigger_adc_by_dma()
561 config->h_dma.config.size = config->size; in ald_adc_timer_trigger_adc_by_dma()
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A Dald_dma.c79 WRITE_REG(DMA->CHANNEL[config->channel].SAR, (uint32_t)config->src); in ald_dma_config_base()
81 …MODIFY_REG(DMA->CHANNEL[config->channel].CON, DMA_CON_SINC_MSK, config->src_inc << DMA_CON_SINC_PO… in ald_dma_config_base()
82 WRITE_REG(DMA->CHANNEL[config->channel].DAR, (uint32_t)config->dst); in ald_dma_config_base()
89 …MODIFY_REG(DMA->CHANNEL[config->channel].NDT, DMA_NDT_TNDT_MSK, config->size << DMA_NDT_TNDT_POSS); in ald_dma_config_base()
150 hperh.config.src = src; in ald_dma_config_basic_easy()
151 hperh.config.dst = dst; in ald_dma_config_basic_easy()
152 hperh.config.size = size; in ald_dma_config_basic_easy()
153 hperh.config.msel = msel; in ald_dma_config_basic_easy()
154 hperh.config.msigsel = msigsel; in ald_dma_config_basic_easy()
155 hperh.config.channel = channel; in ald_dma_config_basic_easy()
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/bsp/samd21/sam_d2x_asflib/sam0/drivers/adc/adc_sam_d_r_h/
A Dadc.c87 Assert(config); in adc_get_config_defaults()
305 config.mux_position = 1; in _adc_configure_ain_pin()
369 (config->reference); in _adc_set_config()
372 switch (config->resolution) { in _adc_set_config()
474 config->clock_prescaler | in _adc_set_config()
587 config->gain_factor | in _adc_set_config()
591 config->negative_input | in _adc_set_config()
592 config->positive_input; in _adc_set_config()
674 struct adc_config *config) in adc_init() argument
679 Assert(config); in adc_init()
[all …]
/bsp/nrf5x/nrf5340/board/
A DKconfig3 config SOC_NRF5340
9 config SOC_NORDIC
17 config BSP_BOARD_PCA_10095
22 config BSP_BOARD_PCA_10143
35 config RT_BSP_LED_PIN
84 config BSP_USING_GPIO
89 config BSP_USING_UART
199 config BSP_USING_IPC
475 config BSP_USING_WDT
514 config BSP_USING_TIM
[all …]
/bsp/nrf5x/nrf52832/board/
A DKconfig3 config SOC_NRF52832
5 config SOC_NRF52832
9 config NRFX_CLOCK_ENABLED
20 config SOC_NORDIC
22 config SOC_NORDIC
35 config BSP_USING_GPIO
44 config BSP_USING_SAADC
160 config BSP_USING_UART
222 config BSP_USING_I2C
264 config BSP_USING_SPI
[all …]
/bsp/rv32m1_vega/rv32m1_sdk_riscv/devices/RV32M1/drivers/
A Dfsl_lpadc.c55 assert(config != NULL); in LPADC_Init()
72 if (config->enableInDozeMode) in LPADC_Init()
104 if (config->enableConvPause) in LPADC_Init()
130 config->powerUpDelay = 0x80; in LPADC_GetDefaultConfig()
135 config->convPauseDelay = 0U; in LPADC_GetDefaultConfig()
136 config->FIFOWatermark = 0U; in LPADC_GetDefaultConfig()
193 config->targetCommandId = 0U; in LPADC_GetDefaultConvTriggerConfig()
194 config->delayPower = 0U; in LPADC_GetDefaultConvTriggerConfig()
195 config->priority = 0U; in LPADC_GetDefaultConvTriggerConfig()
266 config->channelNumber = 0U; in LPADC_GetDefaultConvCommandConfig()
[all …]
/bsp/frdm-k64f/device/MK64F12/
A Dfsl_flexbus.c80 void FLEXBUS_Init(FB_Type *base, const flexbus_config_t *config) in FLEXBUS_Init() argument
82 assert(config != NULL); in FLEXBUS_Init()
83 assert(config->chip < FB_CSAR_COUNT); in FLEXBUS_Init()
84 assert(config->waitStates <= 0x3FU); in FLEXBUS_Init()
119 chip = config->chip; in FLEXBUS_Init()
122 reg_value = config->chipBaseAddress; in FLEXBUS_Init()
130 reg_value |= config->chipBaseAddressMask << FB_CSMR_BAM_SHIFT; in FLEXBUS_Init()
140 reg_value |= (uint32_t)config->portSize << FB_CSCR_PS_SHIFT; in FLEXBUS_Init()
146 reg_value |= (uint32_t)config->waitStates << FB_CSCR_WS_SHIFT; in FLEXBUS_Init()
181 void FLEXBUS_GetDefaultConfig(flexbus_config_t *config) in FLEXBUS_GetDefaultConfig() argument
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