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/bsp/allwinner/libraries/sunxi-hal/hal/source/ccmu/sunxi-ng/
A Dccu.c117 if (!core || index >= core->num_parents || !core->parents) in clk_core_get_parent_by_index()
122 if (!core->parents[index].core) in clk_core_get_parent_by_index()
126 return core->parents[index].core; in clk_core_get_parent_by_index()
458 core->ops->init(core->hw); in __clk_core_init()
465 core->accuracy = core->ops->recalc_accuracy(core->hw, in __clk_core_init()
640 core->clk->core = core; in clk_hw_register()
641 core->clk->name = core->name; in clk_hw_register()
657 hw->core = core; in clk_hw_register()
924 if (core->parents[i].core) in clk_fetch_parent_index()
933 if (core->parents[i].core) in clk_fetch_parent_index()
[all …]
A Dclk.c22 struct clk_core *core = NULL; in clk_get() local
25 core = clk_core_get(type, id); in clk_get()
27 if (!core) in clk_get()
32 clk = core->clk; in clk_get()
57 ret = clk_core_is_enabled(clk->core); in clk_is_enabled()
69 return clk_core_enable(clk->core); in clk_prepare_enable()
76 return clk_core_disable(clk->core); in clk_disable_unprepare()
103 p_clk->core = parent; in clk_get_parent()
121 ret = clk_core_set_parent(clk->core, p_clk->core); in clk_set_parent()
156 return clk_core_set_rate(clk->core, p_clk->core, rate); in clk_set_rate()
[all …]
A Dccu.h96 struct clk_core *core; member
123 struct clk_core *core; member
370 struct clk_core *core; member
797 int __clk_determine_rate(struct clk_hw *core, struct clk_rate_request *req);
813 hal_clk_status_t clk_core_is_enabled(struct clk_core *core);
815 hal_clk_status_t clk_core_enable(struct clk_core *core);
817 hal_clk_status_t clk_core_disable(struct clk_core *core);
819 struct clk_core *clk_core_get_parent(struct clk_core *core);
823 u32 clk_core_get_rate(struct clk_core *core);
827 u32 clk_core_recalc_rate(struct clk_core *core, struct clk_core *p_core);
[all …]
/bsp/wch/arm/
A Dch32f10x_port_cn.md3 + wch\arm\ch32f103c8-core
105 + ch32f103c8-core (具体的BSP名)
106 + ch32f103c8-core\applications
109 + ch32f103c8-core\board
112 + ch32f103c8-core\board\board.c
113 + ch32f103c8-core\board\board.h
116 + ch32f103c8-core\board\Kconfig
118 + ch32f103c8-core\Kconfig
119 + ch32f103c8-core\rtconfig.py
120 + ch32f103c8-core\SConscript
[all …]
/bsp/Infineon/libraries/templates/XMC7200D/libs/TARGET_APP_KIT_XMC72_EVK/COMPONENT_CM0P/
A Dsystem_cm0plus.c400 CY_ASSERT(core < CORE_MAX); in Cy_SysGetCM7Status()
402 if(core == CORE_CM7_0) in Cy_SysGetCM7Status()
407 else if(core == CORE_CM7_1) in Cy_SysGetCM7Status()
427 CY_ASSERT(core < CORE_MAX); in Cy_SysEnableCM7()
437 Cy_SysResetCM7(core); in Cy_SysEnableCM7()
443 if(core == CORE_CM7_0) in Cy_SysEnableCM7()
461 else if(core == CORE_CM7_1) in Cy_SysEnableCM7()
489 CY_ASSERT(core < CORE_MAX); in Cy_SysDisableCM7()
491 if(core == CORE_CM7_0) in Cy_SysDisableCM7()
530 if(core == CORE_CM7_0) in Cy_SysRetainCM7()
[all …]
/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/COMPONENT_CM0P/
A Dsystem_cm0plus.c391 CY_ASSERT(core < CORE_MAX); in Cy_SysGetCM7Status()
393 if(core == CORE_CM7_0) in Cy_SysGetCM7Status()
398 else if(core == CORE_CM7_1) in Cy_SysGetCM7Status()
418 CY_ASSERT(core < CORE_MAX); in Cy_SysEnableCM7()
428 Cy_SysResetCM7(core); in Cy_SysEnableCM7()
434 if(core == CORE_CM7_0) in Cy_SysEnableCM7()
452 else if(core == CORE_CM7_1) in Cy_SysEnableCM7()
480 CY_ASSERT(core < CORE_MAX); in Cy_SysDisableCM7()
482 if(core == CORE_CM7_0) in Cy_SysDisableCM7()
521 if(core == CORE_CM7_0) in Cy_SysRetainCM7()
[all …]
/bsp/Infineon/xmc7200-kit_xmc7200_evk/libs/TARGET_APP_KIT_XMC72_EVK/COMPONENT_CM0P/
A Dsystem_cm0plus.c400 CY_ASSERT(core < CORE_MAX); in Cy_SysGetCM7Status()
402 if(core == CORE_CM7_0) in Cy_SysGetCM7Status()
407 else if(core == CORE_CM7_1) in Cy_SysGetCM7Status()
427 CY_ASSERT(core < CORE_MAX); in Cy_SysEnableCM7()
437 Cy_SysResetCM7(core); in Cy_SysEnableCM7()
443 if(core == CORE_CM7_0) in Cy_SysEnableCM7()
461 else if(core == CORE_CM7_1) in Cy_SysEnableCM7()
489 CY_ASSERT(core < CORE_MAX); in Cy_SysDisableCM7()
491 if(core == CORE_CM7_0) in Cy_SysDisableCM7()
530 if(core == CORE_CM7_0) in Cy_SysRetainCM7()
[all …]
/bsp/allwinner/libraries/sunxi-hal/hal/
A Dlist.txt12 source/sdmmc/core.c
18 source/sound/core/snd_dma.c
19 source/sound/core/snd_params.c
20 source/sound/core/snd_pcm.c
21 source/sound/core/snd_ctl.c
22 source/sound/core/snd_misc.c
23 source/sound/core/snd_core.c
24 source/sound/core/snd_io.c
69 source/usb/core/usb_gen_hub.c
76 source/usb/core/usb_msg.c
[all …]
/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/src/
A Dbl808_l1c.c346 BL_Err_Type ATTR_TCM_SECTION L1C_Set_Cache_Setting_By_ID(uint8_t core, L1C_CACHE_Cfg_Type *cacheSet… in L1C_Set_Cache_Setting_By_ID() argument
348 (void)core; in L1C_Set_Cache_Setting_By_ID()
364 GLB_CORE_ID_Type core = GLB_CORE_ID_INVALID; in L1C_Is_DCache_Range() local
367 core = GLB_Get_Core_Type(); in L1C_Is_DCache_Range()
368 if(core==GLB_CORE_ID_D0){ in L1C_Is_DCache_Range()
393 GLB_CORE_ID_Type core = GLB_CORE_ID_INVALID; in L1C_Get_None_Cache_Addr() local
396 core = GLB_Get_Core_Type(); in L1C_Get_None_Cache_Addr()
397 if(core==GLB_CORE_ID_D0){ in L1C_Get_None_Cache_Addr()
/bsp/core-v-mcu/Libraries/core_v_hal_libraries/
A DSConscript20 bmsis/core-v-mcu/source/core-v-mcu.c
21 bmsis/core-v-mcu/source/crt0.S
22 bmsis/core-v-mcu/source/vectors.S
23 bmsis/core-v-mcu/source/trap_gcc.S
32 cwd + '/bmsis/core-v-mcu/include',
/bsp/Infineon/libraries/templates/XMC7200D/libs/TARGET_APP_KIT_XMC72_EVK/
A Dsystem_cat1c.h485 extern uint32_t Cy_SysGetCM7Status(uint8_t core);
499 extern void Cy_SysEnableCM7(uint8_t core, uint32_t vectorTableOffset);
516 extern void Cy_SysDisableCM7(uint8_t core);
533 extern void Cy_SysRetainCM7(uint8_t core);
550 extern void Cy_SysResetCM7(uint8_t core);
/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/
A Dsystem_cat1c.h489 extern uint32_t Cy_SysGetCM7Status(uint8_t core);
503 extern void Cy_SysEnableCM7(uint8_t core, uint32_t vectorTableOffset);
520 extern void Cy_SysDisableCM7(uint8_t core);
537 extern void Cy_SysRetainCM7(uint8_t core);
554 extern void Cy_SysResetCM7(uint8_t core);
/bsp/Infineon/xmc7200-kit_xmc7200_evk/libs/TARGET_APP_KIT_XMC72_EVK/
A Dsystem_cat1c.h485 extern uint32_t Cy_SysGetCM7Status(uint8_t core);
499 extern void Cy_SysEnableCM7(uint8_t core, uint32_t vectorTableOffset);
516 extern void Cy_SysDisableCM7(uint8_t core);
533 extern void Cy_SysRetainCM7(uint8_t core);
550 extern void Cy_SysResetCM7(uint8_t core);
/bsp/nuvoton/numaker-iot-ma35d1/nuwriter_scripts/
A Dxusbcom.py6 import usb.core
31 except usb.core.USBError as err:
37 except usb.core.USBError as err:
45 except usb.core.USBError as err:
58 except usb.core.USBError as err:
117 self.devices = list(usb.core.find(idVendor=vid, idProduct=pid,
123 except usb.core.NoBackendError as err:
133 except (usb.core.USBError, NotImplementedError) as err:
148 except usb.core.USBError as err:
/bsp/nuvoton/numaker-hmi-ma35d1/nuwriter_scripts/
A Dxusbcom.py6 import usb.core
31 except usb.core.USBError as err:
37 except usb.core.USBError as err:
45 except usb.core.USBError as err:
58 except usb.core.USBError as err:
117 self.devices = list(usb.core.find(idVendor=vid, idProduct=pid,
123 except usb.core.NoBackendError as err:
133 except (usb.core.USBError, NotImplementedError) as err:
148 except usb.core.USBError as err:
/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/src/
A Dbl616_common.c66 void ATTR_TCM_SECTION ASM_Delay_Us(uint32_t core, uint32_t cnt, uint32_t loopT) in ASM_Delay_Us() argument
76 if (core >= 1 * 1000 * 1000) { in ASM_Delay_Us()
78 speed = core / (100 * 1000); in ASM_Delay_Us()
85 speed = core / 1000; in ASM_Delay_Us()
/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/src/
A Dbl602_common.c22 __ASM void ATTR_TCM_SECTION ASM_Delay_Us(uint32_t core, uint32_t cnt) in ASM_Delay_Us() argument
28 void ATTR_TCM_SECTION ASM_Delay_Us(uint32_t core, uint32_t cnt) in ASM_Delay_Us() argument
56 void ATTR_TCM_SECTION ASM_Delay_Us(uint32_t core, uint32_t cnt) in ASM_Delay_Us() argument
105 : "m"(cnt), "m"(core), "m"(divVal) /* input */ in ASM_Delay_Us()
/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/src/
A Dbl702_common.c57 __ASM void ATTR_TCM_SECTION ASM_Delay_Us(uint32_t core, uint32_t cnt) in ASM_Delay_Us() argument
63 void ATTR_TCM_SECTION ASM_Delay_Us(uint32_t core, uint32_t cnt) in ASM_Delay_Us() argument
91 void ATTR_TCM_SECTION ASM_Delay_Us(uint32_t core, uint32_t cnt) in ASM_Delay_Us() argument
140 : "m"(cnt), "m"(core), "m"(divVal) /* input */ in ASM_Delay_Us()
/bsp/core-v-mcu/core-v-cv32e40p/
A DSConstruct39 #SDK_ROOT = E:\rt-thread\bsp\core-v-mcu\core-v-cv32e40p
45 #libraries_path_prefix = E:\rt-thread\bsp\core-v-mcu\Libraries
48 #SDK_LIB = E:\rt-thread\bsp\core-v-mcu\Libraries
59 #libraries_path_prefix = E:\rt-thread\bsp\core-v-mcu\Libraries
/bsp/microchip/samd51-seeed-wio-terminal/bsp/armcc/
A DMakefile47 hpl/core \
53 hpl/core/hpl_core_m4.o \
61 hpl/core/hpl_init.o \
199 …es" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/cmcc" -I"../hpl/core" -I"../hpl/dmac" -I…
208 …es" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/cmcc" -I"../hpl/core" -I"../hpl/dmac" -I…
217 …es" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/cmcc" -I"../hpl/core" -I"../hpl/dmac" -I…
/bsp/microchip/samd51-adafruit-metro-m4/bsp/armcc/
A DMakefile47 hpl/core \
53 hpl/core/hpl_core_m4.o \
61 hpl/core/hpl_init.o \
199 …es" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/cmcc" -I"../hpl/core" -I"../hpl/dmac" -I…
208 …es" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/cmcc" -I"../hpl/core" -I"../hpl/dmac" -I…
217 …es" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/cmcc" -I"../hpl/core" -I"../hpl/dmac" -I…
/bsp/Infineon/psoc6-cy8ckit-062-WIFI-BT/libs/TARGET_CY8CKIT-062-WIFI-BT/deps/
A Dcore-lib.mtbx1 https://github.com/cypresssemiconductorco/core-lib#release-v1.3.1#$$ASSET_REPO$$/core-lib/release-v…
A Dcore-make.mtbx1 https://github.com/cypresssemiconductorco/core-make#release-v3.0.3#$$ASSET_REPO$$/core-make/release…
/bsp/Infineon/psoc6-evaluationkit-062S2/libs/TARGET_RTT-062S2/deps/
A Dcore-lib.mtbx1 https://github.com/cypresssemiconductorco/core-lib#release-v1.4.0#$$ASSET_REPO$$/core-lib/release-v…
A Dcore-make.mtbx1 https://github.com/cypresssemiconductorco/core-make#release-v3.2.1#$$ASSET_REPO$$/core-make/release…

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