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Searched refs:ctrl (Results 1 – 25 of 155) sorted by relevance

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/bsp/loongson/ls1cdev/libraries/
A Dls1c_wdog.c33 unsigned int ctrl; in Wdog_Enable() local
34 ctrl = (WDT_EN); in Wdog_Enable()
35 ctrl |= 0x01; in Wdog_Enable()
37 WDT_EN = ctrl; in Wdog_Enable()
45 ctrl = (WDT_EN); in Wdog_Disable()
46 ctrl &= ~0x01; in Wdog_Disable()
47 WDT_EN = ctrl; in Wdog_Disable()
56 ctrl |= 0x01; in Wdog_Set()
57 WDT_SET = ctrl; in Wdog_Set()
66 ctrl &= ~0x01; in Wdog_Reset()
[all …]
A Dls1c_clock.c54 unsigned int ctrl; in clk_get_pll_rate() local
57 ctrl = reg_read_32((volatile unsigned int *)LS1C_START_FREQ); in clk_get_pll_rate()
58 pll_rate = (((ctrl & M_PLL) >> M_PLL_SHIFT) + ((ctrl & FRAC_N) >> FRAC_N_SHIFT)) * APB_CLK / 4; in clk_get_pll_rate()
71 unsigned int ctrl; in clk_get_cpu_rate() local
77 if (DIV_CPU_SEL & ctrl) // pll分频作为时钟信号 in clk_get_cpu_rate()
79 if (DIV_CPU_EN & ctrl) in clk_get_cpu_rate()
105 unsigned int ctrl; in clk_get_ddr_rate() local
109 ctrl = (ctrl & DIV_SDRAM) >> DIV_SDRAM_SHIFT; in clk_get_ddr_rate()
111 switch (ctrl) in clk_get_ddr_rate()
148 unsigned int ctrl; in clk_get_dc_rate() local
[all …]
A Dls1c_timer.c67 unsigned int ctrl = 0; // ���ƼĴ����еĿ�����Ϣ in timer_init() local
86 ctrl = (1 << LS1C_PWM_INT_LRC_EN) in timer_init()
114 unsigned int ctrl; // ���ƼĴ�����ֵ in timer_is_time_out() local
127 if (ctrl & (1 << LS1C_PWM_INT_SR)) in timer_is_time_out()
212 unsigned int ctrl ; in timer_int_clr() local
221 ctrl = ctrl | (1<<LS1C_PWM_INT_SR) ; in timer_int_clr()
223 ctrl = ctrl & (~(1<<LS1C_PWM_INT_SR)) ; in timer_int_clr()
235 unsigned int ctrl ; in timer_cnt_clr() local
244 ctrl = ctrl | (1<<LS1C_PWM_CNTR_RST); in timer_cnt_clr()
246 ctrl = ctrl & (~(1<<LS1C_PWM_CNTR_RST)) ; in timer_cnt_clr()
[all …]
A Dls1c_i2c.c208 unsigned char ctrl = reg_read_8(i2c_base + LS1C_I2C_CONTROL_OFFSET); in i2c_init() local
212 ctrl = ctrl & ~(LS1C_I2C_CONTROL_EN | LS1C_I2C_CONTROL_IEN); in i2c_init()
213 reg_write_8(ctrl, i2c_base + LS1C_I2C_CONTROL_OFFSET); in i2c_init()
224 ctrl = ctrl | LS1C_I2C_CONTROL_EN; in i2c_init()
225 reg_write_8(ctrl, i2c_base + LS1C_I2C_CONTROL_OFFSET); in i2c_init()
/bsp/at32/libraries/usbotg_library/src/
A Dusbh_ctrl.c412 uhost->ctrl.sts = CTRL_FAIL; in usbh_ctrl_error_handler()
414 uhost->ctrl.err_cnt = 0; in usbh_ctrl_error_handler()
449 uhost->ctrl.sts = CTRL_START; in usbh_ctrl_transfer_loop()
451 switch(uhost->ctrl.state) in usbh_ctrl_transfer_loop()
523 uhost->ctrl.buffer = buffer; in usbh_ctrl_request()
524 uhost->ctrl.len = length; in usbh_ctrl_request()
830 uhost->ctrl.setup.wLength = 0; in usbh_set_configuration()
831 uhost->ctrl.setup.wIndex = 0; in usbh_set_configuration()
851 uhost->ctrl.setup.wLength = 0; in usbh_set_address()
852 uhost->ctrl.setup.wIndex = 0; in usbh_set_address()
[all …]
A Dusbh_core.c439 uhost->ctrl.state = CONTROL_IDLE; in usbh_cfg_default_init()
442 uhost->ctrl.ept0_size = 8; in usbh_cfg_default_init()
452 uhost->ctrl.err_cnt = 0; in usbh_cfg_default_init()
775 uhost->ctrl.state = next_ctrl_state; in usbh_ctrl_result_check()
781 uhost->ctrl.state = CONTROL_IDLE; in usbh_ctrl_result_check()
786 uhost->ctrl.state = next_ctrl_state; in usbh_ctrl_result_check()
821 if(uhost->ctrl.state == CONTROL_IDLE) in usbh_enum_handler()
1028 uhost->ctrl.ept0_size, in usbh_attached()
1034 uhost->ctrl.ept0_size, in usbh_attached()
1107 if(uhost->ctrl.state == CONTROL_IDLE) in usbh_suspend()
[all …]
/bsp/maxim/libraries/MAX32660PeriphDriver/Source/
A Drtc.c48 #define RTC_IS_BUSY (MXC_RTC->ctrl & MXC_F_RTC_CTRL_BUSY)
49 #define RTC_IS_ENABLED (MXC_RTC->ctrl & MXC_F_RTC_CTRL_RTCE)
168 rtc->ctrl |= MXC_F_RTC_CTRL_RTCE; // setting RTCE = 1 in RTC_EnableRTCE()
173 rtc->ctrl &= ~MXC_F_RTC_CTRL_WE; // Prevent Writing... in RTC_EnableRTCE()
191 rtc->ctrl &= ~MXC_F_RTC_CTRL_RTCE; // setting RTCE = 0 in RTC_DisableRTCE()
196 rtc->ctrl &= ~MXC_F_RTC_CTRL_WE; // Prevent Writing... in RTC_DisableRTCE()
215 rtc->ctrl = MXC_F_RTC_CTRL_WE; // Allow Writes in RTC_Init()
311 rtc->ctrl |= MXC_F_RTC_CTRL_WE; in RTC_Trim()
386 if(!(MXC_RTC->ctrl & MXC_F_RTC_CTRL_RDY)) { in RTC_GetTime()
394 if(!(MXC_RTC->ctrl & MXC_F_RTC_CTRL_RDY)) { in RTC_GetTime()
[all …]
A Dwdt.c61 MXC_SETFIELD(wdt->ctrl, MXC_F_WDT_CTRL_INT_PERIOD, period); in WDT_SetIntPeriod()
74 wdt->ctrl |= MXC_F_WDT_CTRL_WDT_EN; in WDT_Enable()
76 wdt->ctrl &= ~(MXC_F_WDT_CTRL_WDT_EN); in WDT_Enable()
84 wdt->ctrl |= MXC_F_WDT_CTRL_INT_EN; in WDT_EnableInt()
86 wdt->ctrl &= ~(MXC_F_WDT_CTRL_INT_EN); in WDT_EnableInt()
94 wdt->ctrl |= MXC_F_WDT_CTRL_RST_EN; in WDT_EnableReset()
96 wdt->ctrl &= ~(MXC_F_WDT_CTRL_RST_EN); in WDT_EnableReset()
110 return !!(wdt->ctrl & MXC_F_WDT_CTRL_RST_FLAG); in WDT_GetResetFlag()
116 wdt->ctrl &= ~(MXC_F_WDT_CTRL_RST_FLAG); in WDT_ClearResetFlag()
122 return !!(wdt->ctrl & MXC_F_WDT_CTRL_INT_FLAG); in WDT_GetIntFlag()
[all …]
A Dspimss.c109 …spi->ctrl = (spi->ctrl & ~(MXC_F_SPIMSS_CTRL_CLKPOL)) | (pol << MXC_F_SPIMSS_CTRL_CLKPOL_POS); //… in SPIMSS_Init()
111 …spi->ctrl = (spi->ctrl & ~(MXC_F_SPIMSS_CTRL_PHASE)) | (pha << MXC_F_SPIMSS_CTRL_PHASE_POS); //… in SPIMSS_Init()
124 spi->ctrl = 0; // Interrupts, SPI transaction all turned off in SPIMSS_Shutdown()
238 spi->ctrl |= (MXC_F_SPIMSS_CTRL_IRQE ); in SPIMSS_Handler()
255 spi->ctrl |= MXC_F_SPIMSS_CTRL_SPIEN; // Enable/Start SPI in SPIMSS_MasterTrans()
278 spi->ctrl |= MXC_F_SPIMSS_CTRL_SPIEN; // Enable/Start SPI in SPIMSS_SlaveTrans()
300 spi->ctrl |= MXC_F_SPIMSS_CTRL_SPIEN; // Enable/Start SPI in SPIMSS_MasterTransAsync()
303 spi->ctrl |= (MXC_F_SPIMSS_CTRL_IRQE | MXC_F_SPIMSS_CTRL_STR); in SPIMSS_MasterTransAsync()
320 spi->ctrl |= MXC_F_SPIMSS_CTRL_SPIEN; // Enable/Start SPI in SPIMSS_SlaveTransAsync()
323 spi->ctrl |= (MXC_F_SPIMSS_CTRL_IRQE ); in SPIMSS_SlaveTransAsync()
[all …]
A Di2c.c171 i2c->ctrl = 0; // clear configuration bits in I2C_Init()
186 i2c->ctrl |= MXC_F_I2C_CTRL_SW_OUT_EN; in I2C_Init()
283 i2c->ctrl = 0; in I2C_Shutdown()
307 i2c->ctrl |= MXC_F_I2C_CTRL_MST; in I2C_MasterWrite()
387 i2c->ctrl |= MXC_F_I2C_CTRL_MST; in I2C_MasterRead()
474 i2c->ctrl &= ~MXC_F_I2C_CTRL_MST; in I2C_Slave()
501 if (i2c->ctrl & MXC_F_I2C_CTRL_READ) { in I2C_Slave()
643 i2c->ctrl |= MXC_F_I2C_CTRL_MST; in I2C_MasterAsync()
928 if (i2c->ctrl & MXC_F_I2C_CTRL_READ) { in I2C_SlaveHandler()
1020 i2c->ctrl = 0; in I2C_Recover()
[all …]
/bsp/loongson/ls1bdev/libraries/
A Dls1b_clock.c40 unsigned int ctrl; in clk_get_pll_rate() local
43 ctrl = reg_read_32((volatile unsigned int *)LS1B_START_FREQ); in clk_get_pll_rate()
44 pll_rate = (12 + (ctrl & 0x3f)) * APB_CLK / 2 in clk_get_pll_rate()
45 + ((ctrl >> 8) & 0x3ff) * APB_CLK / 1024 / 2; in clk_get_pll_rate()
58 unsigned int ctrl; in clk_get_cpu_rate() local
61 ctrl = reg_read_32((volatile unsigned int *)LS1B_CLK_DIV_PARAM); in clk_get_cpu_rate()
62 cpu_rate = pll_rate / ((ctrl & DIV_CPU) >> DIV_CPU_SHIFT); in clk_get_cpu_rate()
75 unsigned int ctrl; in clk_get_ddr_rate() local
78 ctrl = reg_read_32((volatile unsigned int *)LS1B_CLK_DIV_PARAM); in clk_get_ddr_rate()
80 ddr_rate = pll_rate / ((ctrl & DIV_DDR) >> DIV_DDR_SHIFT); in clk_get_ddr_rate()
[all …]
/bsp/rockchip/common/rk_hal/lib/hal/src/
A Dhal_pwm.c144 uint32_t ctrl; in HAL_PWM_SetConfig() local
155 ctrl = READ_REG(PWM_CTRL_REG(pPWM, channel)); in HAL_PWM_SetConfig()
156 ctrl |= PWM_LOCK; in HAL_PWM_SetConfig()
169 ctrl &= ~PWM_LOCK; in HAL_PWM_SetConfig()
188 uint32_t ctrl; in HAL_PWM_SetOneshot() local
211 uint32_t ctrl; in HAL_PWM_SetCapturedFreq() local
219 ctrl &= ~PWM_CTRL_SCALE_MASK; in HAL_PWM_SetCapturedFreq()
220 ctrl |= PWM_LP_ENABLE | PWM_SEL_SCALE_CLK; in HAL_PWM_SetCapturedFreq()
276 uint32_t ctrl; in HAL_PWM_GetMode() local
329 uint32_t ctrl, intEnable; in HAL_PWM_Disable() local
[all …]
/bsp/nxp/lpc/lpc5410x/drivers/
A Ddrv_led.c24 struct led_ctrl ctrl[LED_NUM]; member
43 led.ctrl[0].num = 29; in rt_led_init()
44 led.ctrl[0].port = 0; in rt_led_init()
45 led.ctrl[1].num = 30; in rt_led_init()
46 led.ctrl[1].port = 0; in rt_led_init()
47 led.ctrl[2].num = 31; in rt_led_init()
48 led.ctrl[2].port = 0; in rt_led_init()
76 if ((LPC_GPIO->B[0][led.ctrl[pos + index].num])) in rt_led_read()
149 LPC_GPIO->B[0][led.ctrl[Set_led].num] = 1UL; in Led_Control()
153 LPC_GPIO->B[0][led.ctrl[Set_led].num] = 0UL; in Led_Control()
[all …]
/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/
A Dald_dma.c146 descr->ctrl.next_useburst = 0; in dma_config_base()
149 descr->ctrl.src_prot_ctrl = 0, in dma_config_base()
150 descr->ctrl.dst_prot_ctrl = 0, in dma_config_base()
362 desc->ctrl.src_prot_ctrl = 0; in ald_dma_config_sg_alt_desc()
363 desc->ctrl.dst_prot_ctrl = 0; in ald_dma_config_sg_alt_desc()
755 tmp->ctrl.next_useburst = 0; in ald_dma_config_sg_mem()
758 tmp->ctrl.src_prot_ctrl = 0, in ald_dma_config_sg_mem()
759 tmp->ctrl.dst_prot_ctrl = 0, in ald_dma_config_sg_mem()
814 tmp->ctrl.next_useburst = 0; in ald_dma_config_sg_per()
817 tmp->ctrl.src_prot_ctrl = 0, in ald_dma_config_sg_per()
[all …]
/bsp/nxp/lpc/lpc408x/drivers/
A Ddrv_led.c26 struct led_ctrl ctrl[LED_NUM]; member
43 led.ctrl[3].num = 27; in rt_led_init()
44 led.ctrl[3].port = LPC_GPIO4; in rt_led_init()
45 led.ctrl[2].num = 15; in rt_led_init()
46 led.ctrl[2].port = LPC_GPIO4; in rt_led_init()
47 led.ctrl[1].num = 16; in rt_led_init()
48 led.ctrl[1].port = LPC_GPIO4; in rt_led_init()
49 led.ctrl[0].num = 17; in rt_led_init()
76 if ((led.ctrl[pos + index].port->PIN) & 1 << led.ctrl[pos + index].num) in rt_led_read()
103 led.ctrl[pos + index].port->CLR |= (1 << led.ctrl[pos + index].num); in rt_led_write()
[all …]
/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/
A Dald_dma.c145 descr->ctrl.next_useburst = 0; in dma_config_base()
148 descr->ctrl.src_prot_ctrl = 0, in dma_config_base()
149 descr->ctrl.dst_prot_ctrl = 0, in dma_config_base()
348 desc->ctrl.src_prot_ctrl = 0; in ald_dma_config_sg_alt_desc()
349 desc->ctrl.dst_prot_ctrl = 0; in ald_dma_config_sg_alt_desc()
736 tmp->ctrl.next_useburst = 0; in ald_dma_config_sg_mem()
739 tmp->ctrl.src_prot_ctrl = 0, in ald_dma_config_sg_mem()
740 tmp->ctrl.dst_prot_ctrl = 0, in ald_dma_config_sg_mem()
795 tmp->ctrl.next_useburst = 0; in ald_dma_config_sg_per()
798 tmp->ctrl.src_prot_ctrl = 0, in ald_dma_config_sg_per()
[all …]
/bsp/efm32/Libraries/emlib/src/
A Dem_ebi.c62 uint32_t ctrl = EBI->CTRL; in EBI_Init() local
66 ctrl |= EBI_CTRL_ITS; in EBI_Init()
110 ctrl |= EBI_CTRL_BANK0EN; in EBI_Init()
128 ctrl |= EBI_CTRL_BANK1EN; in EBI_Init()
146 ctrl |= EBI_CTRL_BANK2EN; in EBI_Init()
164 ctrl |= EBI_CTRL_BANK3EN; in EBI_Init()
194 ctrl |= ebiInit->mode; in EBI_Init()
268 EBI->CTRL = ctrl; in EBI_Init()
568 uint32_t ctrl; in EBI_TFTInit() local
597 ctrl = in EBI_TFTInit()
[all …]
/bsp/allwinner/libraries/sunxi-hal/hal/source/usb/uvc/Class/
A Duvc_video.c173 ctrl->dwMaxVideoFrameSize = in uvc_fixup_video_ctrl()
183 ? ctrl->dwFrameInterval in uvc_fixup_video_ctrl()
242 memset(ctrl, 0, sizeof *ctrl); in uvc_get_video_ctrl()
262 ctrl->bFormatIndex = data[2]; in uvc_get_video_ctrl()
263 ctrl->bFrameIndex = data[3]; in uvc_get_video_ctrl()
281 ctrl->bmFramingInfo = 0; in uvc_get_video_ctrl()
282 ctrl->bPreferedVersion = 0; in uvc_get_video_ctrl()
283 ctrl->bMinVersion = 0; in uvc_get_video_ctrl()
284 ctrl->bMaxVersion = 0; in uvc_get_video_ctrl()
317 data[2] = ctrl->bFormatIndex; in uvc_set_video_ctrl()
[all …]
/bsp/loongson/ls1bdev/drivers/
A Ddisplay_controller.c49 int pll,ctrl,div,div1,frac; in caclulate_freq() local
52 ctrl = PLL_DIV_PARAM; in caclulate_freq()
53 rt_kprintf("pll=0x%x, ctrl=0x%x\n", pll, ctrl); in caclulate_freq()
72 ctrl = ctrl&~(0x1f<<26)|(div1<<26)|(1<<31); in caclulate_freq()
81 ctrl = ctrl&~(0x1f<<26)|(div<<26)|(1<<31); in caclulate_freq()
86 ctrl = ctrl&~(0x1f<<26)|((div+1)<<26)|(1<<31); in caclulate_freq()
90 rt_kprintf("new pll=0x%x, ctrl=0x%x\n", pll, ctrl); in caclulate_freq()
91 ctrl |= 0x2a00; in caclulate_freq()
92 PLL_DIV_PARAM = ctrl; in caclulate_freq()
/bsp/nxp/lpc/lpc43xx/drivers/
A Ddrv_led.c40 struct led_ctrl ctrl[LED_NUM]; member
61 led.ctrl[0].num = LED1_PIN; in rt_led_init()
62 led.ctrl[0].port = LED1_PORT; in rt_led_init()
63 led.ctrl[1].num = LED2_PIN; in rt_led_init()
64 led.ctrl[1].port = LED2_PORT; in rt_led_init()
91 … if ((LPC_GPIO_PORT->PIN[led.ctrl[pos + index].port] & (1 << led.ctrl[pos + index].num)) != 0) in rt_led_read()
118 LPC_GPIO_PORT->CLR[led.ctrl[pos + index].port] = (1 << led.ctrl[pos + index].num); in rt_led_write()
122 LPC_GPIO_PORT->SET[led.ctrl[pos + index].port] = (1 << led.ctrl[pos + index].num); in rt_led_write()
/bsp/xplorer4330/drivers/
A Ddrv_led.c32 struct led_ctrl ctrl[LED_NUM]; member
54 led.ctrl[0].num = LED1_PIN; in rt_led_init()
55 led.ctrl[0].port = LED1_PORT; in rt_led_init()
56 led.ctrl[1].num = LED2_PIN; in rt_led_init()
57 led.ctrl[1].port = LED2_PORT; in rt_led_init()
84 … if ((LPC_GPIO_PORT->PIN[led.ctrl[pos + index].port] & (1 << led.ctrl[pos + index].num)) != 0) in rt_led_read()
111 LPC_GPIO_PORT->CLR[led.ctrl[pos + index].port] = (1 << led.ctrl[pos + index].num); in rt_led_write()
115 LPC_GPIO_PORT->SET[led.ctrl[pos + index].port] = (1 << led.ctrl[pos + index].num); in rt_led_write()
/bsp/hpmicro/libraries/hpm_sdk/drivers/src/
A Dhpm_uart_drv.c372 | UART_FCRR_TFIFOT4_SET(ctrl->tx_fifo_level) in uart_config_fifo_ctrl()
374 | UART_FCRR_DMAE_SET(ctrl->dma_enable) in uart_config_fifo_ctrl()
377 | UART_FCRR_FIFOE_SET(ctrl->fifo_enable); in uart_config_fifo_ctrl()
379 ptr->FCR = UART_FCR_TFIFOT_SET(ctrl->tx_fifo_level) in uart_config_fifo_ctrl()
380 | UART_FCR_RFIFOT_SET(ctrl->rx_fifo_level) in uart_config_fifo_ctrl()
383 | UART_FCR_DMAE_SET(ctrl->dma_enable) in uart_config_fifo_ctrl()
384 | UART_FCR_FIFOE_SET(ctrl->fifo_enable); in uart_config_fifo_ctrl()
386 ptr->GPR = UART_FCR_TFIFOT_SET(ctrl->tx_fifo_level) in uart_config_fifo_ctrl()
387 | UART_FCR_RFIFOT_SET(ctrl->rx_fifo_level) in uart_config_fifo_ctrl()
388 | UART_FCR_DMAE_SET(ctrl->dma_enable) in uart_config_fifo_ctrl()
[all …]
/bsp/phytium/board/
A Dboard.c96 u64 ctrl = gtimer_get_control(); in GenericTimerInterruptEnable() local
97 if (ctrl & CNTP_CTL_IMASK) in GenericTimerInterruptEnable()
99 ctrl &= ~CNTP_CTL_IMASK; in GenericTimerInterruptEnable()
100 gtimer_set_control(ctrl); in GenericTimerInterruptEnable()
106 u32 ctrl = gtimer_get_control(); /* get CNTP_CTL */ in GenericTimerStart() local
108 if (!(ctrl & CNTP_CTL_ENABLE)) in GenericTimerStart()
110 ctrl |= CNTP_CTL_ENABLE; /* enable gtimer if off */ in GenericTimerStart()
111 gtimer_set_control(ctrl); /* set CNTP_CTL */ in GenericTimerStart()
/bsp/rockchip/common/rk_hal/lib/hal/src/pinctrl/
A Dhal_pinctrl.c74 const struct HAL_PINCTRL_DEV *ctrl = PINCTRL_GetInfo(); in PINCTRL_AcquireMuxRoute() local
79 if (ctrl->muxRouteDataNum == 0) { in PINCTRL_AcquireMuxRoute()
84 for (i = 0; i < ctrl->muxRouteDataNum; i++) { in PINCTRL_AcquireMuxRoute()
85 data = &ctrl->muxRouteData[i]; in PINCTRL_AcquireMuxRoute()
92 if (i >= ctrl->muxRouteDataNum) { in PINCTRL_AcquireMuxRoute()
118 const struct HAL_PINCTRL_DEV *ctrl = PINCTRL_GetInfo(); in PINCTRL_RectifyMuxParams() local
123 if (ctrl->muxRecalDataNum == 0) { in PINCTRL_RectifyMuxParams()
128 for (i = 0; i < ctrl->muxRecalDataNum; i++) { in PINCTRL_RectifyMuxParams()
129 data = &ctrl->muxRecalData[i]; in PINCTRL_RectifyMuxParams()
136 if (i >= ctrl->muxRecalDataNum) { in PINCTRL_RectifyMuxParams()
[all …]
/bsp/synwit/libraries/SWM341_CSL/SWM341_UsbHost_Lib/HID/
A Dusbh_hid_keybd.c150 void USBH_HID_KeyBD_Handle(uint8_t ctrl, char key) in USBH_HID_KeyBD_Handle() argument
152 if((ctrl & KBD_LEFT_CTRL) | (ctrl & KBD_RIGHT_CTRL)) in USBH_HID_KeyBD_Handle()
155 if((ctrl & KBD_LEFT_ALT) | (ctrl & KBD_RIGHT_ALT)) in USBH_HID_KeyBD_Handle()

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