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Searched refs:ctrl_pin_value (Results 1 – 3 of 3) sorted by relevance

/bsp/hpmicro/libraries/hpm_sdk/components/ppi/
A Dhpm_ppi.c99 cmd_config.ctrl_pin_value[config->wel_ctrl_pin] = true; in ppi_config_async_sram()
108 cmd_config.ctrl_pin_value[config->adv_ctrl_pin] = config->addr_valid_polarity; in ppi_config_async_sram()
110 cmd_config.ctrl_pin_value[config->rel_ctrl_pin] = true; in ppi_config_async_sram()
122 cmd_config.ctrl_pin_value[config->rel_ctrl_pin] = true; in ppi_config_async_sram()
134 cmd_config.ctrl_pin_value[config->rel_ctrl_pin] = false; in ppi_config_async_sram()
146 cmd_config.ctrl_pin_value[config->rel_ctrl_pin] = true; in ppi_config_async_sram()
189 cmd_config.ctrl_pin_value[config->rel_ctrl_pin] = true; in ppi_config_async_sram()
200 cmd_config.ctrl_pin_value[config->wel_ctrl_pin] = true; in ppi_config_async_sram()
212 cmd_config.ctrl_pin_value[config->wel_ctrl_pin] = true; in ppi_config_async_sram()
224 cmd_config.ctrl_pin_value[config->wel_ctrl_pin] = false; in ppi_config_async_sram()
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/bsp/hpmicro/libraries/hpm_sdk/drivers/src/
A Dhpm_ppi_drv.c94 tmp = PPI_CMD_CTRL_CFG_IO_CFG7_SET(config->ctrl_pin_value[7]) in ppi_config_cmd()
95 | PPI_CMD_CTRL_CFG_IO_CFG6_SET(config->ctrl_pin_value[6]) in ppi_config_cmd()
96 | PPI_CMD_CTRL_CFG_IO_CFG5_SET(config->ctrl_pin_value[5]) in ppi_config_cmd()
97 | PPI_CMD_CTRL_CFG_IO_CFG4_SET(config->ctrl_pin_value[4]) in ppi_config_cmd()
98 | PPI_CMD_CTRL_CFG_IO_CFG3_SET(config->ctrl_pin_value[3]) in ppi_config_cmd()
99 | PPI_CMD_CTRL_CFG_IO_CFG2_SET(config->ctrl_pin_value[2]) in ppi_config_cmd()
100 | PPI_CMD_CTRL_CFG_IO_CFG1_SET(config->ctrl_pin_value[1]) in ppi_config_cmd()
101 | PPI_CMD_CTRL_CFG_IO_CFG0_SET(config->ctrl_pin_value[0]); in ppi_config_cmd()
/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/
A Dhpm_ppi_drv.h162 bool ctrl_pin_value[8]; member

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