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Searched refs:ctrla (Results 1 – 16 of 16) sorted by relevance

/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/usart/
A Dusart.c72 uint32_t ctrla = 0; in _usart_set_config() local
109 ctrla = (uint32_t)config->data_order | in _usart_set_config()
180 ctrla |= transfer_mode; in _usart_set_config()
183 ctrla |= SERCOM_USART_CTRLA_MODE(0x1); in _usart_set_config()
186 ctrla |= SERCOM_USART_CTRLA_MODE(0x0); in _usart_set_config()
229 ctrla |= SERCOM_USART_CTRLA_FORM(1); in _usart_set_config()
236 ctrla |= SERCOM_USART_CTRLA_FORM(0); in _usart_set_config()
239 ctrla |= SERCOM_USART_CTRLA_FORM(0); in _usart_set_config()
253 ctrla |= config->lin_node; in _usart_set_config()
259 ctrla |= SERCOM_USART_CTRLA_RUNSTDBY; in _usart_set_config()
[all …]
/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/spi/
A Dspi.c222 uint32_t ctrla = 0; in _spi_set_config() local
267 ctrla |= config->data_order; in _spi_set_config()
270 ctrla |= config->transfer_mode; in _spi_set_config()
273 ctrla |= config->mux_setting; in _spi_set_config()
280 ctrla |= SERCOM_SPI_CTRLA_RUNSTDBY; in _spi_set_config()
300 spi_module->CTRLA.reg |= ctrla; in _spi_set_config()
366 uint32_t ctrla = 0; in _spi_check_config() local
416 ctrla |= config->data_order; in _spi_check_config()
419 ctrla |= config->transfer_mode; in _spi_check_config()
422 ctrla |= config->mux_setting; in _spi_check_config()
[all …]
/bsp/samd21/sam_d2x_asflib/sam0/drivers/i2s/
A Di2s.c75 uint32_t ctrla; in i2s_init() local
76 ctrla = module_inst->hw->CTRLA.reg; in i2s_init()
77 if (ctrla & I2S_CTRLA_ENABLE) { in i2s_init()
78 if (ctrla & (I2S_CTRLA_SEREN1 | in i2s_init()
148 uint32_t ctrla, syncbusy; in i2s_clock_unit_set_config() local
150 ctrla = module_inst->hw->CTRLA.reg; in i2s_clock_unit_set_config()
157 if (ctrla & (I2S_CTRLA_CKEN0 << clock_unit)) { in i2s_clock_unit_set_config()
264 uint32_t ctrla, syncbusy; in i2s_serializer_set_config() local
266 ctrla = module_inst->hw->CTRLA.reg; in i2s_serializer_set_config()
273 if (ctrla & (I2S_CTRLA_CKEN0 << serializer)) { in i2s_serializer_set_config()
/bsp/samd21/sam_d2x_asflib/sam0/drivers/tcc/
A Dtcc.c288 uint32_t ctrla = 0; in _tcc_build_ctrla() local
299 ctrla |= (TCC_CTRLA_CPTEN0 << i); in _tcc_build_ctrla()
304 ctrla |= TCC_CTRLA_RUNSTDBY; in _tcc_build_ctrla()
306 ctrla |= config->counter.reload_action << TCC_CTRLA_PRESCSYNC_Pos; in _tcc_build_ctrla()
307 ctrla |= config->counter.clock_prescaler << TCC_CTRLA_PRESCALER_Pos; in _tcc_build_ctrla()
309 *value_buffer = ctrla; in _tcc_build_ctrla()
552 uint32_t ctrla = 0; in tcc_init() local
553 status = _tcc_build_ctrla(module_index, config, &ctrla); in tcc_init()
624 hw->CTRLA.reg = ctrla; in tcc_init()
/bsp/microchip/samd51-adafruit-metro-m4/bsp/hpl/sercom/
A Dhpl_sercom.c2071 uint32_t ctrla; member
2261 uint32_t ctrla; in _spi_set_mode() local
2267 ctrla = hri_sercomspi_read_CTRLA_reg(hw); in _spi_set_mode()
2269 ctrla |= (mode & 0x3u) << SERCOM_SPI_CTRLA_CPHA_Pos; in _spi_set_mode()
2270 hri_sercomspi_write_CTRLA_reg(hw, ctrla); in _spi_set_mode()
2327 uint32_t ctrla; in _spi_set_data_order() local
2333 ctrla = hri_sercomspi_read_CTRLA_reg(hw); in _spi_set_data_order()
2336 ctrla |= SERCOM_SPI_CTRLA_DORD; in _spi_set_data_order()
2338 ctrla &= ~SERCOM_SPI_CTRLA_DORD; in _spi_set_data_order()
2340 hri_sercomspi_write_CTRLA_reg(hw, ctrla); in _spi_set_data_order()
[all …]
/bsp/microchip/samc21/bsp/hpl/sercom/
A Dhpl_sercom.c2124 uint32_t ctrla; member
2308 uint32_t ctrla; in _spi_set_mode() local
2314 ctrla = hri_sercomspi_read_CTRLA_reg(hw); in _spi_set_mode()
2316 ctrla |= (mode & 0x3u) << SERCOM_SPI_CTRLA_CPHA_Pos; in _spi_set_mode()
2317 hri_sercomspi_write_CTRLA_reg(hw, ctrla); in _spi_set_mode()
2374 uint32_t ctrla; in _spi_set_data_order() local
2380 ctrla = hri_sercomspi_read_CTRLA_reg(hw); in _spi_set_data_order()
2383 ctrla |= SERCOM_SPI_CTRLA_DORD; in _spi_set_data_order()
2385 ctrla &= ~SERCOM_SPI_CTRLA_DORD; in _spi_set_data_order()
2387 hri_sercomspi_write_CTRLA_reg(hw, ctrla); in _spi_set_data_order()
[all …]
/bsp/microchip/samd51-seeed-wio-terminal/bsp/hpl/sercom/
A Dhpl_sercom.c2071 uint32_t ctrla; member
2261 uint32_t ctrla; in _spi_set_mode() local
2267 ctrla = hri_sercomspi_read_CTRLA_reg(hw); in _spi_set_mode()
2269 ctrla |= (mode & 0x3u) << SERCOM_SPI_CTRLA_CPHA_Pos; in _spi_set_mode()
2270 hri_sercomspi_write_CTRLA_reg(hw, ctrla); in _spi_set_mode()
2327 uint32_t ctrla; in _spi_set_data_order() local
2333 ctrla = hri_sercomspi_read_CTRLA_reg(hw); in _spi_set_data_order()
2336 ctrla |= SERCOM_SPI_CTRLA_DORD; in _spi_set_data_order()
2338 ctrla &= ~SERCOM_SPI_CTRLA_DORD; in _spi_set_data_order()
2340 hri_sercomspi_write_CTRLA_reg(hw, ctrla); in _spi_set_data_order()
[all …]
/bsp/microchip/saml10/bsp/hpl/sercom/
A Dhpl_sercom.c2071 uint32_t ctrla; member
2261 uint32_t ctrla; in _spi_set_mode() local
2267 ctrla = hri_sercomspi_read_CTRLA_reg(hw); in _spi_set_mode()
2269 ctrla |= (mode & 0x3u) << SERCOM_SPI_CTRLA_CPHA_Pos; in _spi_set_mode()
2270 hri_sercomspi_write_CTRLA_reg(hw, ctrla); in _spi_set_mode()
2327 uint32_t ctrla; in _spi_set_data_order() local
2333 ctrla = hri_sercomspi_read_CTRLA_reg(hw); in _spi_set_data_order()
2336 ctrla |= SERCOM_SPI_CTRLA_DORD; in _spi_set_data_order()
2338 ctrla &= ~SERCOM_SPI_CTRLA_DORD; in _spi_set_data_order()
2340 hri_sercomspi_write_CTRLA_reg(hw, ctrla); in _spi_set_data_order()
[all …]
/bsp/microchip/same54/bsp/hpl/sercom/
A Dhpl_sercom.c2144 uint32_t ctrla; member
2334 uint32_t ctrla; in _spi_set_mode() local
2340 ctrla = hri_sercomspi_read_CTRLA_reg(hw); in _spi_set_mode()
2342 ctrla |= (mode & 0x3u) << SERCOM_SPI_CTRLA_CPHA_Pos; in _spi_set_mode()
2343 hri_sercomspi_write_CTRLA_reg(hw, ctrla); in _spi_set_mode()
2400 uint32_t ctrla; in _spi_set_data_order() local
2406 ctrla = hri_sercomspi_read_CTRLA_reg(hw); in _spi_set_data_order()
2409 ctrla |= SERCOM_SPI_CTRLA_DORD; in _spi_set_data_order()
2411 ctrla &= ~SERCOM_SPI_CTRLA_DORD; in _spi_set_data_order()
2413 hri_sercomspi_write_CTRLA_reg(hw, ctrla); in _spi_set_data_order()
[all …]
/bsp/microchip/samc21/bsp/hpl/dmac/
A Dhpl_dmac.c67 uint8_t ctrla; member
108 hri_dmac_write_CHCTRLA_RUNSTDBY_bit(DMAC, _cfgs[i].ctrla & DMAC_CHCTRLA_RUNSTDBY); in _dma_init()
/bsp/microchip/samd51-seeed-wio-terminal/bsp/hpl/dmac/
A Dhpl_dmac.c69 uint32_t ctrla; member
107 hri_dmac_write_CHCTRLA_reg(DMAC, i, _cfgs[i].ctrla); in _dma_init()
/bsp/microchip/saml10/bsp/hpl/dmac/
A Dhpl_dmac.c67 uint8_t ctrla; member
104 hri_dmac_write_CHCTRLA_RUNSTDBY_bit(DMAC, _cfgs[i].ctrla & DMAC_CHCTRLA_RUNSTDBY); in _dma_init()
/bsp/microchip/same54/bsp/hpl/dmac/
A Dhpl_dmac.c69 uint32_t ctrla; member
107 hri_dmac_write_CHCTRLA_reg(DMAC, i, _cfgs[i].ctrla); in _dma_init()
/bsp/microchip/samd51-adafruit-metro-m4/bsp/hpl/dmac/
A Dhpl_dmac.c69 uint32_t ctrla; member
107 hri_dmac_write_CHCTRLA_reg(DMAC, i, _cfgs[i].ctrla); in _dma_init()
/bsp/microchip/samd51-adafruit-metro-m4/bsp/hpl/usb/
A Dhpl_usb.c1503 uint8_t ctrla; in _usb_d_dev_enable() local
1508 ctrla = hri_usbdevice_read_CTRLA_reg(hw); in _usb_d_dev_enable()
1509 if ((ctrla & USB_CTRLA_ENABLE) == 0) { in _usb_d_dev_enable()
1510 hri_usbdevice_write_CTRLA_reg(hw, ctrla | USB_CTRLA_ENABLE); in _usb_d_dev_enable()
1528 uint8_t ctrla; in _usb_d_dev_disable() local
1534 ctrla = hri_usbdevice_read_CTRLA_reg(hw); in _usb_d_dev_disable()
1535 if (ctrla & USB_CTRLA_ENABLE) { in _usb_d_dev_disable()
1536 hri_usbdevice_write_CTRLA_reg(hw, ctrla & ~USB_CTRLA_ENABLE); in _usb_d_dev_disable()
/bsp/microchip/samd51-seeed-wio-terminal/bsp/hpl/usb/
A Dhpl_usb.c1503 uint8_t ctrla; in _usb_d_dev_enable() local
1508 ctrla = hri_usbdevice_read_CTRLA_reg(hw); in _usb_d_dev_enable()
1509 if ((ctrla & USB_CTRLA_ENABLE) == 0) { in _usb_d_dev_enable()
1510 hri_usbdevice_write_CTRLA_reg(hw, ctrla | USB_CTRLA_ENABLE); in _usb_d_dev_enable()
1528 uint8_t ctrla; in _usb_d_dev_disable() local
1534 ctrla = hri_usbdevice_read_CTRLA_reg(hw); in _usb_d_dev_disable()
1535 if (ctrla & USB_CTRLA_ENABLE) { in _usb_d_dev_disable()
1536 hri_usbdevice_write_CTRLA_reg(hw, ctrla & ~USB_CTRLA_ENABLE); in _usb_d_dev_disable()

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