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Searched refs:div1 (Results 1 – 6 of 6) sorted by relevance

/bsp/rv32m1_vega/ri5cy/board/
A Dclock_config.c69 .div1 = kSCG_AsyncClkDisable, in CLOCK_CONFIG_FircSafeConfig()
144 ….div1 = kSCG_AsyncClkDisable, /* System OSC Clock Divider 1: Clock output is disabled …
151 … .div1 = kSCG_AsyncClkDisable, /* Slow IRC Clock Divider 1: Clock output is disabled */
159 .div1 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 1: divided by 1 */
168 .div1 = kSCG_AsyncClkDivBy1, /* Low Power FLL Clock Divider 1: divided by 1 */
251 ….div1 = kSCG_AsyncClkDisable, /* System OSC Clock Divider 1: Clock output is disabled …
258 … .div1 = kSCG_AsyncClkDisable, /* Slow IRC Clock Divider 1: Clock output is disabled */
266 .div1 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 1: divided by 1 */
366 ….div1 = kSCG_AsyncClkDisable, /* System OSC Clock Divider 1: Clock output is disabled …
373 .div1 = kSCG_AsyncClkDivBy1, /* Slow IRC Clock Divider 1: divided by 1 */
[all …]
A Dboard.c42 .div1 = kSCG_AsyncClkDivBy1, /* Low Power FLL Clock Divider 1: Clock output is disabled */
/bsp/loongson/ls1bdev/drivers/
A Ddisplay_controller.c49 int pll,ctrl,div,div1,frac; in caclulate_freq() local
63 div1 = clk1/(long)PCLK/1000; in caclulate_freq()
64 if (div!=div1) in caclulate_freq()
68 if (div!=div1) in caclulate_freq()
70 frac = ((PCLK*1000*div1)*2*1024/33333333 - (12+i+(pll&0x3f))*1024)&0x3ff; in caclulate_freq()
72 ctrl = ctrl&~(0x1f<<26)|(div1<<26)|(1<<31); in caclulate_freq()
/bsp/rockchip/common/rk_hal/lib/hal/src/pm/
A Dhal_pm_rk2108.c135 uint32_t div1, div2, div; in PM_GetPllPostDivEven() local
146 div1 = div / div2; in PM_GetPllPostDivEven()
147 if (div1 <= 7) { in PM_GetPllPostDivEven()
152 if (div1 < div2) { in PM_GetPllPostDivEven()
156 *postDiv1 = div1; in PM_GetPllPostDivEven()
159 if ((div1 * div2) != div) { in PM_GetPllPostDivEven()
/bsp/rv32m1_vega/rv32m1_sdk_riscv/devices/RV32M1/drivers/
A Dfsl_clock.c338 …SCG_SOSCDIV_SOSCDIV1(config->div1) | SCG_SOSCDIV_SOSCDIV2(config->div2) | SCG_SOSCDIV_SOSCDIV3(con… in CLOCK_InitSysOsc()
444 …SCG_SIRCDIV_SIRCDIV1(config->div1) | SCG_SIRCDIV_SIRCDIV2(config->div2) | SCG_SIRCDIV_SIRCDIV3(con… in CLOCK_InitSirc()
545 …SCG_FIRCDIV_FIRCDIV1(config->div1) | SCG_FIRCDIV_FIRCDIV2(config->div2) | SCG_FIRCDIV_FIRCDIV3(con… in CLOCK_InitFirc()
683 SCG->LPFLLDIV = SCG_LPFLLDIV_LPFLLDIV1(config->div1) | SCG_LPFLLDIV_LPFLLDIV2(config->div2) | in CLOCK_InitLpFll()
A Dfsl_clock.h539 scg_async_clk_div_t div1; /*!< SOSCDIV1 value. */ member
568 scg_async_clk_div_t div1; /*!< SIRCDIV1 value. */ member
653 scg_async_clk_div_t div1; /*!< FIRCDIV1 value. */ member
736 scg_async_clk_div_t div1; /*!< LPFLLDIV1 value. */ member

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