Searched refs:div2 (Results 1 – 5 of 5) sorted by relevance
| /bsp/rv32m1_vega/ri5cy/board/ |
| A D | clock_config.c | 70 .div2 = kSCG_AsyncClkDivBy2, in CLOCK_CONFIG_FircSafeConfig()
145 ….div2 = kSCG_AsyncClkDisable, /* System OSC Clock Divider 2: Clock output is disabled …
152 … .div2 = kSCG_AsyncClkDisable, /* Slow IRC Clock Divider 2: Clock output is disabled */
160 .div2 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 2: divided by 1 */
169 ….div2 = kSCG_AsyncClkDisable, /* Low Power FLL Clock Divider 2: Clock output is disabl…
252 ….div2 = kSCG_AsyncClkDisable, /* System OSC Clock Divider 2: Clock output is disabled …
259 … .div2 = kSCG_AsyncClkDisable, /* Slow IRC Clock Divider 2: Clock output is disabled */
267 .div2 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 2: divided by 1 */
367 ….div2 = kSCG_AsyncClkDisable, /* System OSC Clock Divider 2: Clock output is disabled …
374 .div2 = kSCG_AsyncClkDivBy1, /* Slow IRC Clock Divider 2: divided by 1 */
[all …]
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| A D | board.c | 43 .div2 = kSCG_AsyncClkDisable, /* Low Power FLL Clock Divider 2: Clock output is disabled */
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| /bsp/rockchip/common/rk_hal/lib/hal/src/pm/ |
| A D | hal_pm_rk2108.c | 135 uint32_t div1, div2, div; in PM_GetPllPostDivEven() local
145 for (div2 = 2; div2 <= 6;) { in PM_GetPllPostDivEven()
146 div1 = div / div2; in PM_GetPllPostDivEven()
150 div2 += 2; in PM_GetPllPostDivEven()
152 if (div1 < div2) { in PM_GetPllPostDivEven()
157 *postDiv2 = div2; in PM_GetPllPostDivEven()
159 if ((div1 * div2) != div) { in PM_GetPllPostDivEven()
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| /bsp/rv32m1_vega/rv32m1_sdk_riscv/devices/RV32M1/drivers/ |
| A D | fsl_clock.c | 338 …SCG_SOSCDIV_SOSCDIV1(config->div1) | SCG_SOSCDIV_SOSCDIV2(config->div2) | SCG_SOSCDIV_SOSCDIV3(con… in CLOCK_InitSysOsc()
444 …SCG_SIRCDIV_SIRCDIV1(config->div1) | SCG_SIRCDIV_SIRCDIV2(config->div2) | SCG_SIRCDIV_SIRCDIV3(con… in CLOCK_InitSirc()
545 …SCG_FIRCDIV_FIRCDIV1(config->div1) | SCG_FIRCDIV_FIRCDIV2(config->div2) | SCG_FIRCDIV_FIRCDIV3(con… in CLOCK_InitFirc()
683 SCG->LPFLLDIV = SCG_LPFLLDIV_LPFLLDIV1(config->div1) | SCG_LPFLLDIV_LPFLLDIV2(config->div2) | in CLOCK_InitLpFll()
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| A D | fsl_clock.h | 540 scg_async_clk_div_t div2; /*!< SOSCDIV2 value. */ member
569 scg_async_clk_div_t div2; /*!< SIRCDIV2 value. */ member
654 scg_async_clk_div_t div2; /*!< FIRCDIV2 value. */ member
737 scg_async_clk_div_t div2; /*!< LPFLLDIV2 value. */ member
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