Searched refs:div2_en (Results 1 – 2 of 2) sorted by relevance
| /bsp/avr32/software_framework/drivers/pm/ |
| A D | pm_conf_clocks.c | 70 unsigned long mul, div, div2_en = 0, div2_cpu = 0, div2_pba = 0; in pm_configure_clocks() local
126 div2_en = 1; in pm_configure_clocks()
129 pll_freq = in_osc0_f * mul / (div * (1 << div2_en)); in pm_configure_clocks()
147 , div2_en // pll_div2 in pm_configure_clocks()
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| A D | power_clocks_lib.c | 318 unsigned long mul, div, div2_en = 0, div2_cpu = 0, div2_pba = 0; in pcl_configure_clocks_uc3c() local
378 div2_en = 1; in pcl_configure_clocks_uc3c()
381 pll_freq = in_osc0_f * mul / (div * (1 << div2_en)); in pcl_configure_clocks_uc3c()
393 …opt.pll_div2 = div2_en, // pll_div2 Divide the PLL output frequency by 2 (this settings doe… in pcl_configure_clocks_uc3c()
482 unsigned long mul, div, div2_en = 0, div2_cpu = 0, div2_pba = 0; in pcl_configure_clocks_uc3d() local
542 div2_en = 1; in pcl_configure_clocks_uc3d()
545 pll_freq = in_osc0_f * mul / (div * (1 << div2_en)); in pcl_configure_clocks_uc3d()
557 …opt.pll_div2 = div2_en, // pll_div2 Divide the PLL output frequency by 2 (this settings doe… in pcl_configure_clocks_uc3d()
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