Searched refs:div3 (Results 1 – 4 of 4) sorted by relevance
| /bsp/rv32m1_vega/ri5cy/board/ |
| A D | clock_config.c | 146 ….div3 = kSCG_AsyncClkDisable, /* System OSC Clock Divider 3: Clock output is disabled …
153 .div3 = kSCG_AsyncClkDivBy1, /* Slow IRC Clock Divider 3: divided by 1 */
161 .div3 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 3: divided by 1 */
170 ….div3 = kSCG_AsyncClkDisable, /* Low Power FLL Clock Divider 3: Clock output is disabl…
253 ….div3 = kSCG_AsyncClkDisable, /* System OSC Clock Divider 3: Clock output is disabled …
260 .div3 = kSCG_AsyncClkDivBy1, /* Slow IRC Clock Divider 3: divided by 1 */
268 .div3 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 3: divided by 1 */
277 ….div3 = kSCG_AsyncClkDisable, /* Low Power FLL Clock Divider 3: Clock output is disabl…
368 ….div3 = kSCG_AsyncClkDisable, /* System OSC Clock Divider 3: Clock output is disabled …
375 .div3 = kSCG_AsyncClkDivBy1, /* Slow IRC Clock Divider 3: divided by 1 */
[all …]
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| A D | board.c | 44 .div3 = kSCG_AsyncClkDisable, /* Low Power FLL Clock Divider 3: Clock output is disabled */
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| /bsp/rv32m1_vega/rv32m1_sdk_riscv/devices/RV32M1/drivers/ |
| A D | fsl_clock.c | 338 …V_SOSCDIV1(config->div1) | SCG_SOSCDIV_SOSCDIV2(config->div2) | SCG_SOSCDIV_SOSCDIV3(config->div3); in CLOCK_InitSysOsc()
444 …V_SIRCDIV1(config->div1) | SCG_SIRCDIV_SIRCDIV2(config->div2) | SCG_SIRCDIV_SIRCDIV3(config->div3); in CLOCK_InitSirc()
545 …V_FIRCDIV1(config->div1) | SCG_FIRCDIV_FIRCDIV2(config->div2) | SCG_FIRCDIV_FIRCDIV3(config->div3); in CLOCK_InitFirc()
684 SCG_LPFLLDIV_LPFLLDIV3(config->div3); in CLOCK_InitLpFll()
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| A D | fsl_clock.h | 541 scg_async_clk_div_t div3; /*!< SOSCDIV3 value. */ member
570 scg_async_clk_div_t div3; /*!< SIRCDIV3 value. */ member
655 scg_async_clk_div_t div3; /*!< FIRCDIV3 value. */ member
738 scg_async_clk_div_t div3; /*!< LPFLLDIV3 value. */ member
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