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Searched refs:divCore (Results 1 – 3 of 3) sorted by relevance

/bsp/rv32m1_vega/ri5cy/board/
A Dclock_config.c74 .divCore = kSCG_SysClkDivBy1, /* Core clock divider. */ in CLOCK_CONFIG_FircSafeConfig()
136 .divCore = kSCG_SysClkDivBy1, /* Core Clock Divider: divided by 1 */
243 .divCore = kSCG_SysClkDivBy1, /* Core Clock Divider: divided by 1 */
358 .divCore = kSCG_SysClkDivBy2, /* Core Clock Divider: divided by 2 */
/bsp/rv32m1_vega/rv32m1_sdk_riscv/devices/RV32M1/drivers/
A Dfsl_clock.c300 freq /= (sysClkConfig.divCore + 1U); /* divided by the DIVCORE firstly. */ in CLOCK_GetSysClkFreq()
A Dfsl_clock.h467 uint32_t divCore : 4; /*!< Core clock divider, see @ref scg_sys_clk_div_t. */ member

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