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/bsp/rv32m1_vega/ri5cy/board/
A Dclock_config.c73 .divSlow = kSCG_SysClkDivBy4, /* Slow clock divider. */ in CLOCK_CONFIG_FircSafeConfig()
133 .divSlow = kSCG_SysClkDivBy2, /* Slow Clock Divider: divided by 2 */
240 .divSlow = kSCG_SysClkDivBy9, /* Slow Clock Divider: divided by 9 */
355 .divSlow = kSCG_SysClkDivBy9, /* Slow Clock Divider: divided by 9 */
/bsp/rv32m1_vega/rv32m1_sdk_riscv/devices/RV32M1/drivers/
A Dfsl_clock.c304 freq /= (sysClkConfig.divSlow + 1U); in CLOCK_GetSysClkFreq()
A Dfsl_clock.h463 uint32_t divSlow : 4; /*!< Slow clock divider, see @ref scg_sys_clk_div_t. */ member

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