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Searched refs:divide (Results 1 – 10 of 10) sorted by relevance

/bsp/frdm-k64f/device/MK64F12/
A Dfsl_sai.c121 uint16_t fract, divide; in SAI_SetMasterClockDivider() local
145 divide = mul_freq / mclk_Hz; in SAI_SetMasterClockDivider()
159 divide += 1; in SAI_SetMasterClockDivider()
166 current_divide = divide; in SAI_SetMasterClockDivider()
/bsp/hpmicro/hpm6300evk/board/debug_scripts/openocd/boards/
A Dhpm6300evk.cfg29 # 133Mhz pll1_clk0: 266Mhz divide by 2
32 # 166Mhz pll2_clk0: 333Mhz divide by 2
/bsp/hpmicro/hpm6750evkmini/board/debug_scripts/openocd/boards/
A Dhpm6750evkmini.cfg75 # 133Mhz pll1_clk0: 266Mhz divide by 2
78 # 166Mhz pll2_clk0: 333Mhz divide by 2
/bsp/allwinner/libraries/sunxi-hal/hal/source/disp2/disp/de/
A Ddisp_hdmi.c114 bool divide = false; in hdmi_is_divide_by() local
122 divide = true; in hdmi_is_divide_by()
124 return divide; in hdmi_is_divide_by()
/bsp/hpmicro/hpm6750evk/board/debug_scripts/openocd/boards/
A Dhpm6750evk.cfg75 # 133Mhz pll1_clk0: 266Mhz divide by 2
78 # 166Mhz pll2_clk0: 333Mhz divide by 2
/bsp/hpmicro/hpm6750evk2/board/debug_scripts/openocd/boards/
A Dhpm6750evk2.cfg75 # 133Mhz pll1_clk0: 266Mhz divide by 2
78 # 166Mhz pll2_clk0: 333Mhz divide by 2
/bsp/beaglebone/
A DAM335x_sk_DDR3.mac90 //set multiply and divide values
130 //set multiply and divide values
/bsp/nxp/imx/imxrt/imxrt1060-nxp-evk/
A Devkmimxrt1060_sdram_init.mac79 // PERCLK_PODF: 1 divide by 2
/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/
A DRelease_Notes.txt1936 + Remove unnecessary divide/mod operation ("ring_buffer.c", "ht32_serial.c").
/bsp/hpmicro/libraries/hpm_sdk/
A DCHANGELOG.md495 - middleware: hpm_mcl: fix divide-by-zero error. refs: hpm_sdk-#1091

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