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Searched refs:dmc_init_config (Results 1 – 4 of 4) sorted by relevance

/bsp/apm32/apm32e103ze-evalboard/board/ports/
A Ddrv_sdram.c133 DMC_Config_T dmc_init_config; in SDRAM_Init() local
157 dmc_init_config.bankWidth = DMC_BANK_WIDTH_1; //!< Configure bank address width in SDRAM_Init()
159 dmc_init_config.bankWidth = DMC_BANK_WIDTH_2; //!< Configure bank address width in SDRAM_Init()
161 dmc_init_config.clkPhase = DMC_CLK_PHASE_REVERSE; //!< Configure clock phase in SDRAM_Init()
162 dmc_init_config.rowWidth = SDRAM_ROW_BITS; //!< Configure row address width in SDRAM_Init()
163 dmc_init_config.colWidth = SDRAM_COLUMN_BITS; //!< Configure column address width in SDRAM_Init()
164 dmc_init_config.memorySize = SDRAM_MEMORY_SIZE; in SDRAM_Init()
165 dmc_init_config.timing = dmc_timing_config; in SDRAM_Init()
167 DMC_Config(&dmc_init_config); in SDRAM_Init()
/bsp/apm32/libraries/Drivers/drv_sdram/APM32E1/
A Ddrv_sdram.c133 DMC_Config_T dmc_init_config; in SDRAM_Init() local
157 dmc_init_config.bankWidth = DMC_BANK_WIDTH_1; //!< Configure bank address width in SDRAM_Init()
159 dmc_init_config.bankWidth = DMC_BANK_WIDTH_2; //!< Configure bank address width in SDRAM_Init()
161 dmc_init_config.clkPhase = DMC_CLK_PHASE_REVERSE; //!< Configure clock phase in SDRAM_Init()
162 dmc_init_config.rowWidth = SDRAM_ROW_BITS; //!< Configure row address width in SDRAM_Init()
163 dmc_init_config.colWidth = SDRAM_COLUMN_BITS; //!< Configure column address width in SDRAM_Init()
164 dmc_init_config.memorySize = SDRAM_MEMORY_SIZE; in SDRAM_Init()
165 dmc_init_config.timing = dmc_timing_config; in SDRAM_Init()
167 DMC_Config(&dmc_init_config); in SDRAM_Init()
/bsp/apm32/apm32f407zg-evalboard/board/ports/
A Ddrv_sdram.c123 DMC_Config_T dmc_init_config; in SDRAM_Init() local
147 dmc_init_config.bankWidth = DMC_BANK_WIDTH_1; //!< Configure bank address width in SDRAM_Init()
149 dmc_init_config.bankWidth = DMC_BANK_WIDTH_2; //!< Configure bank address width in SDRAM_Init()
151 dmc_init_config.clkPhase = DMC_CLK_PHASE_REVERSE; //!< Configure clock phase in SDRAM_Init()
152 dmc_init_config.rowWidth = SDRAM_ROW_BITS; //!< Configure row address width in SDRAM_Init()
153 dmc_init_config.colWidth = SDRAM_COLUMN_BITS; //!< Configure column address width in SDRAM_Init()
154 dmc_init_config.timing = dmc_timing_config; in SDRAM_Init()
156 DMC_Config(&dmc_init_config); in SDRAM_Init()
/bsp/apm32/libraries/Drivers/drv_sdram/APM32F4/
A Ddrv_sdram.c123 DMC_Config_T dmc_init_config; in SDRAM_Init() local
147 dmc_init_config.bankWidth = DMC_BANK_WIDTH_1; //!< Configure bank address width in SDRAM_Init()
149 dmc_init_config.bankWidth = DMC_BANK_WIDTH_2; //!< Configure bank address width in SDRAM_Init()
151 dmc_init_config.clkPhase = DMC_CLK_PHASE_REVERSE; //!< Configure clock phase in SDRAM_Init()
152 dmc_init_config.rowWidth = SDRAM_ROW_BITS; //!< Configure row address width in SDRAM_Init()
153 dmc_init_config.colWidth = SDRAM_COLUMN_BITS; //!< Configure column address width in SDRAM_Init()
154 dmc_init_config.timing = dmc_timing_config; in SDRAM_Init()
156 DMC_Config(&dmc_init_config); in SDRAM_Init()

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