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Searched refs:dram_gate_adr (Results 1 – 2 of 2) sorted by relevance

/bsp/allwinner/libraries/sunxi-hal/hal/source/disp2/disp/de/lowlevel_v2x/
A Dde_clock.c26 .dram_gate_adr = 0x00,
45 .dram_gate_adr = 0x00,
60 .dram_gate_adr = 0x00,
154 readl(de_clk_tbl[i].dram_gate_adr in __de_clk_enable()
160 de_clk_tbl[i].dram_gate_adr + de_base); in __de_clk_enable()
181 readl(de_clk_tbl[i].dram_gate_adr in __de_clk_disable()
187 de_clk_tbl[i].dram_gate_adr + de_base); in __de_clk_disable()
A Dde_clock.h32 u32 dram_gate_adr; member

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