Home
last modified time | relevance | path

Searched refs:dsi_ctl1 (Results 1 – 2 of 2) sorted by relevance

/bsp/allwinner/libraries/sunxi-hal/hal/source/disp2/disp/de/lowlevel_v2x/
A Dde_dsi_28.c587 dsi_dev[sel]->dsi_ctl1.bits.phy_clk_lane_enable = 1; in dsi_hs_clk()
809 dsi_dev[sel]->dsi_ctl1.bits.phy_rst = 0; in dsi_dphy_cfg()
811 dsi_dev[sel]->dsi_ctl1.bits.phy_en = 0; in dsi_dphy_cfg()
835 dsi_dev[sel]->dsi_ctl1.bits.phy_rst = 1; in dsi_dphy_cfg()
837 dsi_dev[sel]->dsi_ctl1.bits.phy_clk_gating = 1; in dsi_dphy_cfg()
839 dsi_dev[sel]->dsi_ctl1.bits.phy_en = 1; in dsi_dphy_cfg()
842 dsi_dev[sel]->dsi_ctl1.bits.phy_lane_num = lane - 1; in dsi_dphy_cfg()
855 dsi_dev[sel]->dsi_ctl1.bits.phy_clk_gating = 0; in dsi_io_close()
857 dsi_dev[sel]->dsi_ctl1.bits.phy_rst = 0; in dsi_io_close()
859 dsi_dev[sel]->dsi_ctl1.bits.phy_en = 0; in dsi_io_close()
[all …]
A Dde_dsi_type_28.h558 union DSI_CTL1_t dsi_ctl1; member

Completed in 11 milliseconds