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Searched refs:enableMode (Results 1 – 8 of 8) sorted by relevance

/bsp/rv32m1_vega/ri5cy/board/
A Dclock_config.c68 const scg_sirc_config_t scgSircConfig = {.enableMode = kSCG_SircEnable, in CLOCK_CONFIG_FircSafeConfig()
143 .enableMode = SCG_SOSC_DISABLE, /* System OSC disabled */
150 ….enableMode = kSCG_SircEnable | kSCG_SircEnableInLowPower,/* Enable SIRC clock, Enable SIRC in low…
158 .enableMode = kSCG_FircEnable, /* Enable FIRC clock */
167 .enableMode = SCG_LPFLL_DISABLE, /* LPFLL clock disabled */
250 .enableMode = SCG_SOSC_DISABLE, /* System OSC disabled */
265 .enableMode = kSCG_FircEnable, /* Enable FIRC clock */
274 .enableMode = kSCG_LpFllEnable, /* Enable LPFLL clock */
365 .enableMode = SCG_SOSC_DISABLE, /* System OSC disabled */
380 .enableMode = kSCG_FircEnable, /* Enable FIRC clock */
[all …]
A Dboard.c41 .enableMode = kSCG_LpFllEnable, /* LPFLL clock disabled */
/bsp/frdm-k64f/board/
A Dclock_config.c165 .enableMode = MCG_PLL_DISABLE, /* MCGPLLCLK disabled */
183 ….enableMode = kOSC_ErClkEnable, /* Enable external reference clock, disable external reference c…
263 .enableMode = MCG_PLL_DISABLE, /* MCGPLLCLK disabled */
281 .enableMode = OSC_ER_CLK_DISABLE, /* Disable external reference clock */
/bsp/nxp/mcx/mcxc/frdm-mcxc444/board/MCUX_Config/board/
A Dclock_config.c113 ….enableMode = kOSC_ErClkEnable, /* Enable external reference clock, disable external reference c…
179 .enableMode = OSC_ER_CLK_DISABLE, /* Disable external reference clock */
/bsp/frdm-k64f/device/MK64F12/
A Dfsl_clock.h483 uint8_t enableMode; /*!< OSCERCLK enable mode. OR'ed value of @ref _oscer_enable_mode. */ member
639 uint8_t enableMode; /*!< Enable mode. OR'ed value of @ref _mcg_pll_enable_mode. */ member
1012 status_t CLOCK_SetInternalRefClkConfig(uint8_t enableMode, mcg_irc_mode_t ircs, uint8_t fcrdiv);
1191 reg |= config->enableMode; in OSC_SetExtRefClkConfig()
A Dfsl_clock.c689 status_t CLOCK_SetInternalRefClkConfig(uint8_t enableMode, mcg_irc_mode_t ircs, uint8_t fcrdiv) in CLOCK_SetInternalRefClkConfig() argument
724 MCG->C1 = (MCG->C1 & ~(MCG_C1_IRCLKEN_MASK | MCG_C1_IREFSTEN_MASK)) | (uint8_t)enableMode; in CLOCK_SetInternalRefClkConfig()
727 if ((mcgOutClkState == kMCG_ClkOutStatInt) || (enableMode & kMCG_IrclkEnable)) in CLOCK_SetInternalRefClkConfig()
846 MCG->C5 |= ((uint32_t)kMCG_PllEnableIndependent | (uint32_t)config->enableMode); in CLOCK_EnablePll0()
1789 if (config->pll0Config.enableMode & kMCG_PllEnableIndependent) in CLOCK_SetMcgConfig()
/bsp/rv32m1_vega/rv32m1_sdk_riscv/devices/RV32M1/drivers/
A Dfsl_clock.c344 tmp8 = config->enableMode; in CLOCK_InitSysOsc()
450 SCG->SIRCCSR = SCG_SIRCCSR_SIRCEN_MASK | config->enableMode; in CLOCK_InitSirc()
573 SCG->FIRCCSR |= (SCG_FIRCCSR_FIRCEN_MASK | SCG_FIRCCSR_FIRCTREN_MASK | config->enableMode); in CLOCK_InitFirc()
711 SCG->LPFLLCSR |= (SCG_LPFLLCSR_LPFLLEN_MASK | config->enableMode); in CLOCK_InitLpFll()
A Dfsl_clock.h537 uint8_t enableMode; /*!< Enable mode, OR'ed value of _scg_sosc_enable_mode. */ member
567 uint32_t enableMode; /*!< Enable mode, OR'ed value of _scg_sirc_enable_mode. */ member
651 uint32_t enableMode; /*!< Enable mode, OR'ed value of _scg_firc_enable_mode. */ member
734 uint8_t enableMode; /*!< Enable mode, OR'ed value of _scg_lpfll_enable_mode */ member

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