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Searched refs:factor (Results 1 – 25 of 28) sorted by relevance

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/bsp/allwinner/libraries/sunxi-hal/hal/source/ccmu/sunxi/
A Dclk_factors.c40 switch (factor->lock_mode) in sunxi_clk_disable_plllock()
132 config = factor->config; in sunxi_clk_fators_enable()
135 reg = readl(factor->reg); in sunxi_clk_fators_enable()
259 config = factor->config; in sunxi_clk_fators_is_enabled()
286 if (!factor->calc_rate) in sunxi_clk_factors_recalc_rate()
366 if (factor->calc_rate) in sunxi_clk_factors_recalc_rate()
499 if (!factor->get_factors || !factor->calc_rate) in sunxi_clk_factors_round_rate()
527 factor->frac_mode = (table[index].factor >> f_config->modeshift) & 1; in sunxi_clk_get_common_factors()
528 factor->frac_freq = (table[index].factor >> f_config->outshift) & 1; in sunxi_clk_get_common_factors()
610 factor->frac_mode = (table[i].factor >> f_config->modeshift) & 1; in sunxi_clk_com_ftr_sr()
[all …]
A Dclk_factors.h39 u32 factor; member
262 int (*get_factors)(u32 rate, u32 parent_rate, struct clk_factors_value *factor);
263 int (*calc_rate)(u32 parent_rate, struct clk_factors_value *factor);
276 struct clk_factors_value *factor,
/bsp/allwinner/libraries/sunxi-hal/hal/source/ccmu/sunxi/sun8iw19p1/
A Dclk_sun8iw19.c999 if (!factor) in get_factors_pll_cpu()
1021 if (!factor) in get_factors_pll_ddr()
1044 if (!factor) in get_factors_pll_periph0()
1067 if (!factor) in get_factors_pll_periph1()
1090 if (!factor) in get_factors_pll_video()
1121 if (!factor) in get_factors_pll_csi()
1143 do_div(tmp_rate, (factor->factord1 + 1) * (factor->factord2 + 1)); in calc_rate_pll_csi()
1163 do_div(tmp_rate, (factor->factord1 + 1) * (factor->factord2 + 1)); in calc_rate_pll_ddr()
1173 do_div(tmp_rate, 2 * (factor->factord1 + 1) * (factor->factord2 + 1)); in calc_rate_pll_periph0()
1182 do_div(tmp_rate, 2 * (factor->factord1 + 1) * (factor->factord2 + 1)); in calc_rate_pll_periph1()
[all …]
/bsp/allwinner/libraries/sunxi-hal/hal/source/ccmu/sunxi/sun8iw18p1/
A Dclk_sun8iw18.c754 if (!factor) in get_factors_pll_cpu()
776 if (!factor) in get_factors_pll_ddr()
799 if (!factor) in get_factors_pll_periph0()
822 if (!factor) in get_factors_pll_periph1()
855 do_div(tmp_rate, (factor->factord1 + 1) * (factor->factord2 + 1)); in calc_rate_pll_ddr()
865 do_div(tmp_rate, 2 * (factor->factord1 + 1) * (factor->factord2 + 1)); in calc_rate_pll_periph0()
874 do_div(tmp_rate, 2 * (factor->factord1 + 1) * (factor->factord2 + 1)); in calc_rate_pll_periph1()
919 factor->factorn = 21; in get_factors_pll_audio()
920 factor->factorp = 11; in get_factors_pll_audio()
921 factor->factord1 = 0; in get_factors_pll_audio()
[all …]
/bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/include/
A Dhal_fll.h147 #define FLL_STATUS_MULT_FACTOR_SET(dst,src,factor) (__BITINSERT((dst),(src),16,0)) argument
148 #define FLL_STATUS_MULT_FACTOR(factor) ((factor) << 16) argument
153 #define FLL_CONF1_MODE(factor) ((factor) << 31) argument
157 #define FLL_CONF1_LOCK(factor) ((factor) << 30) argument
161 #define FLL_CONF1_DIV(factor) ((factor) << 26) argument
165 #define FLL_CONF1_DCO(factor) ((factor) << 16) argument
169 #define FLL_CONF1_MULT_FACTOR(factor) ((factor) << 0) argument
/bsp/efm32/Libraries/emlib/src/
A Dem_usart.c240 uint32_t factor; in USART_BaudrateCalc() local
264 factor = 128; in USART_BaudrateCalc()
285 factor = 256 / 16; in USART_BaudrateCalc()
290 factor = 256 / 8; in USART_BaudrateCalc()
295 factor = 256 / 2; in USART_BaudrateCalc()
300 factor = 256 / 4; in USART_BaudrateCalc()
335 br = factor * quotient; in USART_BaudrateCalc()
342 br += (factor * remainder) / divisor; in USART_BaudrateCalc()
/bsp/rockchip/rk3500/driver/clk/
A Dclk-mmc-phase.c114 rt_ubase_t factor = (ROCKCHIP_MMC_DELAY_ELEMENT_PSEC / 10) * in rk_clk_mmc_get_phase() local
119 degrees += RT_DIV_ROUND_CLOSEST(delay_num * factor, 1000000); in rk_clk_mmc_get_phase()
/bsp/maxim/libraries/MAX32660PeriphDriver/Source/
A Duart.c108 int32_t factor = -1; in UART_Init() local
141 factor += 1; in UART_Init()
142 baud0 = div >> (7-factor); // divide by 128,64,32,16 to extract integer part in UART_Init()
143 baud1 = ((div << factor) - (baud0 << 7)); //subtract factor corrected div - integer parts in UART_Init()
144 } while ((baud0 == 0) && (factor < MAX_FACTOR)); in UART_Init()
146 uart->baud0 = ((factor << MXC_F_UART_BAUD0_FACTOR_POS) | baud0); in UART_Init()
/bsp/n32/libraries/N32G4FR_Firmware_Library/CMSIS/device/
A Dsystem_n32g4fr.c99 #error Cannot make a PLL multiply factor to SYSCLK_FREQ.
120 #error Cannot make a PLL multiply factor to SYSCLK_FREQ.
/bsp/n32/libraries/N32G45x_Firmware_Library/CMSIS/device/
A Dsystem_n32g45x.c99 #error Cannot make a PLL multiply factor to SYSCLK_FREQ.
120 #error Cannot make a PLL multiply factor to SYSCLK_FREQ.
/bsp/n32/libraries/N32WB452_Firmware_Library/CMSIS/device/
A Dsystem_n32wb452.c99 #error Cannot make a PLL multiply factor to SYSCLK_FREQ.
120 #error Cannot make a PLL multiply factor to SYSCLK_FREQ.
/bsp/n32g452xx/Libraries/N32_Std_Driver/CMSIS/device/
A Dsystem_n32g45x.c99 #error Cannot make a PLL multiply factor to SYSCLK_FREQ.
120 #error Cannot make a PLL multiply factor to SYSCLK_FREQ.
/bsp/allwinner/libraries/sunxi-hal/hal/source/ccmu/sunxi-ng/
A DMakefile19 obj-y += clk-fixed-factor.o
/bsp/allwinner/libraries/sunxi-hal/hal/source/g2d_rcq/
A Dg2d_driver_i.h108 unsigned int factor; member
/bsp/n32/libraries/N32L43x_Firmware_Library/CMSIS/device/
A Dsystem_n32l43x.c149 #error Cannot make a PLL multiply factor to SYSCLK_FREQ.
179 #error Cannot make a PLL multiply factor to SYSCLK_FREQ.
/bsp/n32/libraries/N32L40x_Firmware_Library/CMSIS/device/
A Dsystem_n32l40x.c150 #error Cannot make a PLL multiply factor to SYSCLK_FREQ.
180 #error Cannot make a PLL multiply factor to SYSCLK_FREQ.
/bsp/n32/libraries/N32G43x_Firmware_Library/CMSIS/device/
A Dsystem_n32g43x.c149 #error Cannot make a PLL multiply factor to SYSCLK_FREQ.
179 #error Cannot make a PLL multiply factor to SYSCLK_FREQ.
/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/src/
A Dbl808_uhs_phy.c1992 uint32_t factor = 0; in GLB_Config_UHS_PLL_Freq() local
2043 factor = pllFreq*20480/(xtalFreq/uhsPllMCfg.clkpllRefdivRatio); in GLB_Config_UHS_PLL_Freq()
2044 if(factor<32*2048){ in GLB_Config_UHS_PLL_Freq()
2046 }else if(factor<64*2048){ in GLB_Config_UHS_PLL_Freq()
2048 }else if(factor<128*2048){ in GLB_Config_UHS_PLL_Freq()
2074 uhsPllCfg[GLB_XTAL_24M].clkpllSdmin = factor; in GLB_Config_UHS_PLL_Freq()
2075 uhsPllCfg[GLB_XTAL_32M].clkpllSdmin = factor; in GLB_Config_UHS_PLL_Freq()
2076 uhsPllCfg[GLB_XTAL_38P4M].clkpllSdmin = factor; in GLB_Config_UHS_PLL_Freq()
2077 uhsPllCfg[GLB_XTAL_40M].clkpllSdmin = factor; in GLB_Config_UHS_PLL_Freq()
2078 uhsPllCfg[GLB_XTAL_26M].clkpllSdmin = factor; in GLB_Config_UHS_PLL_Freq()
[all …]
/bsp/Infineon/psoc6-cy8cproto-062S3-4343W/libs/TARGET_CY8CPROTO-062S3-4343W/
A DREADME.md5 …3, 512-Mb Quad-SPI NOR flash. This kit is designed with a snap-away form-factor, allowing the user…
A DRELEASE.md2 …3, 512-Mb Quad-SPI NOR flash. This kit is designed with a snap-away form-factor, allowing the user…
/bsp/nxp/mcx/mcxc/frdm-mcxc444/
A DREADME_EN.md4 … designed for rapid prototyping and features a compact and scalable form factor. The board provide…
/bsp/microchip/same70/
A DREADME_zh.md39 … inputs per PWM for motor control, two external triggers to manage power factor correction (PFC), …
A DREADME.md39 … inputs per PWM for motor control, two external triggers to manage power factor correction (PFC), …
/bsp/allwinner/libraries/sunxi-hal/hal/
A DSConscript11 source/ccmu/sunxi-ng/clk-fixed-factor.c
/bsp/simulator/SDL2/include/
A DSDL_opengles2_gl2.h455 typedef void (GL_APIENTRYP PFNGLPOLYGONOFFSETPROC) (GLfloat factor, GLfloat units);
598 GL_APICALL void GL_APIENTRY glPolygonOffset (GLfloat factor, GLfloat units);

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