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Searched refs:fbdiv (Results 1 – 9 of 9) sorted by relevance

/bsp/hpmicro/libraries/hpm_sdk/drivers/src/
A Dhpm_pllctl_drv.c87 uint32_t freq, fbdiv, refdiv, postdiv; in pllctl_init_int_pll_with_freq() local
97 if (fbdiv > PLLCTL_INT_PLL_MAX_FBDIV) { in pllctl_init_int_pll_with_freq()
102 if (fbdiv > PLLCTL_INT_PLL_MAX_FBDIV) { in pllctl_init_int_pll_with_freq()
108 } else if (fbdiv < PLLCTL_INT_PLL_MIN_FBDIV) { in pllctl_init_int_pll_with_freq()
113 if (fbdiv < PLLCTL_INT_PLL_MIN_FBDIV) { in pllctl_init_int_pll_with_freq()
123 || (fbdiv > PLLCTL_INT_PLL_MAX_FBDIV) in pllctl_init_int_pll_with_freq()
124 || (fbdiv < PLLCTL_INT_PLL_MIN_FBDIV) in pllctl_init_int_pll_with_freq()
154 uint32_t frac, refdiv, fbdiv, freq, postdiv; in pllctl_init_frac_pll_with_freq() local
166 if (fbdiv > PLLCTL_FRAC_PLL_MAX_FBDIV) { in pllctl_init_frac_pll_with_freq()
200 frac = (uint32_t)((div - fbdiv) * (1 << 24)); in pllctl_init_frac_pll_with_freq()
[all …]
/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/
A Dhpm_pllctl_drv.h219 static inline hpm_stat_t pllctl_set_fbdiv_int(PLLCTL_Type *ptr, uint8_t pll, uint16_t fbdiv) in pllctl_set_fbdiv_int() argument
222 …|| ((fbdiv - 1) > (uint16_t)(PLLCTL_PLL_CFG2_FBDIV_INT_MASK >> PLLCTL_PLL_CFG2_FBDIV_INT_SHIFT))) { in pllctl_set_fbdiv_int()
226 …tr->PLL[pll].CFG2 & ~(PLLCTL_PLL_CFG2_FBDIV_INT_MASK))) | PLLCTL_PLL_CFG2_FBDIV_INT_SET(fbdiv - 1); in pllctl_set_fbdiv_int()
242 static inline hpm_stat_t pllctl_set_fbdiv_frac(PLLCTL_Type *ptr, uint8_t pll, uint16_t fbdiv) in pllctl_set_fbdiv_frac() argument
245 …|| ((fbdiv - 1) > (uint16_t) (PLLCTL_PLL_FREQ_FBDIV_FRAC_MASK >> PLLCTL_PLL_FREQ_FBDIV_FRAC_SHIFT)… in pllctl_set_fbdiv_frac()
250 | PLLCTL_PLL_FREQ_FBDIV_FRAC_SET(fbdiv - 1); in pllctl_set_fbdiv_frac()
/bsp/rockchip/rk3500/driver/clk/
A Dclk-pll-rk3568.c176 rate_table->fbdiv = foutvco / clk_gcd; in rk_pll_clk_set_by_auto()
184 rate_table->fbdiv = foutvco / MHZ / clk_gcd; in rk_pll_clk_set_by_auto()
255 (rate->postdiv1 << PLLCON0_POSTDIV1_SHIFT) |rate->fbdiv); in rk_pll_set_rate()
285 rt_uint32_t refdiv, fbdiv, postdiv1, postdiv2, dsmpd, frac; in rk_pll_get_rate() local
303 fbdiv = (con & PLLCON0_FBDIV_MASK) >> PLLCON0_FBDIV_SHIFT; in rk_pll_get_rate()
310 rate = (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000; in rk_pll_get_rate()
A Dclk-rk3568.h40 rt_uint32_t fbdiv; member
92 .fbdiv = _fbdiv, \
A Dclk-rk3588.h45 rt_uint32_t fbdiv; member
117 .fbdiv = _fbdiv, \
A Dclk-pll-rk3588.c208 rate_table->fbdiv = foutvco / clk_gcd; in rk_pll_clk_set_by_auto()
216 rate_table->fbdiv = foutvco / MHZ / clk_gcd; in rk_pll_clk_set_by_auto()
350 (rate->postdiv1 << RK3036_PLLCON0_POSTDIV1_SHIFT) |rate->fbdiv); in rk3036_pll_set_rate()
380 rt_uint32_t refdiv, fbdiv, postdiv1, postdiv2, dsmpd, frac; in rk3036_pll_get_rate() local
398 fbdiv = (con & RK3036_PLLCON0_FBDIV_MASK) >> RK3036_PLLCON0_FBDIV_SHIFT; in rk3036_pll_get_rate()
405 rate = (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000; in rk3036_pll_get_rate()
/bsp/k230/drivers/interdrv/sysctl/sysctl_clock/
A Dsysctl_clk.c533 uint32_t fbdiv; /* feedback clock divide */ in sysctl_boot_get_root_clk_freq() local
557 fbdiv = (sysctl_boot->pll[0].cfg0 >> 0) & 0x1FFF; /* bit 0~12 */ in sysctl_boot_get_root_clk_freq()
558 … freq = (double)OSC_CLOCK_FREQ_24M * (double)(fbdiv+1) / (double)(refdiv+1) / (double)(outdiv+1); in sysctl_boot_get_root_clk_freq()
586 fbdiv = (sysctl_boot->pll[1].cfg0 >> 0) & 0x1FFF; /* bit 0~12 */ in sysctl_boot_get_root_clk_freq()
587 … freq = (double)OSC_CLOCK_FREQ_24M * (double)(fbdiv+1) / (double)(refdiv+1) / (double)(outdiv+1); in sysctl_boot_get_root_clk_freq()
615 fbdiv = (sysctl_boot->pll[2].cfg0 >> 0) & 0x1FFF; /* bit 0~12 */ in sysctl_boot_get_root_clk_freq()
616 … freq = (double)OSC_CLOCK_FREQ_24M * (double)(fbdiv+1) / (double)(refdiv+1) / (double)(outdiv+1); in sysctl_boot_get_root_clk_freq()
644 fbdiv = (sysctl_boot->pll[3].cfg0 >> 0) & 0x1FFF; /* bit 0~12 */ in sysctl_boot_get_root_clk_freq()
645 … freq = (double)OSC_CLOCK_FREQ_24M * (double)(fbdiv+1) / (double)(refdiv+1) / (double)(outdiv+1); in sysctl_boot_get_root_clk_freq()
672 bool sysctl_boot_set_root_clk_freq(sysctl_clk_node_e clk, uint32_t fbdiv, uint32_t refdiv, uint32_t… in sysctl_boot_set_root_clk_freq() argument
[all …]
A Dsysctl_clk.h568 bool sysctl_boot_set_root_clk_freq(sysctl_clk_node_e clk, uint32_t fbdiv, uint32_t refdiv, uint32_t…
/bsp/rockchip/common/rk_hal/lib/hal/src/cru/
A Dhal_cru_rk2108.c744 uint32_t frac, fbdiv; in HAL_CRU_PllCompensation() local
767 fbdiv = READ_REG(*conOffset0) & 0xfff; in HAL_CRU_PllCompensation()
771 fracdiv = (m / MHZ) + ((n / MHZ) * fbdiv) + frac; in HAL_CRU_PllCompensation()

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