| /bsp/allwinner/libraries/sunxi-hal/hal/source/ccmu/sunxi/ |
| A D | clk_periph.c | 92 struct sunxi_clk_periph_gate *gate = &periph->gate; in __sunxi_clk_periph_enable_shared() local
135 struct sunxi_clk_periph_gate *gate = &periph->gate; in __sunxi_clk_periph_enable() local
148 reg = readl(gate->bus); in __sunxi_clk_periph_enable()
150 writel(reg, gate->bus); in __sunxi_clk_periph_enable()
213 gate = &periph->gate; in sunxi_clk_periph_is_enabled()
218 if (gate->bus) in sunxi_clk_periph_is_enabled()
225 if (gate->enable) in sunxi_clk_periph_is_enabled()
232 if (gate->reset) in sunxi_clk_periph_is_enabled()
239 if (gate->dram) in sunxi_clk_periph_is_enabled()
254 struct sunxi_clk_periph_gate *gate = &periph->gate; in __sunxi_clk_periph_disable_shared() local
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| A D | clk_periph.h | 56 .gate = { \
210 struct sunxi_clk_periph_gate gate; member
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| /bsp/rockchip/common/drivers/ |
| A D | drv_clock.c | 81 if (!gate) in clk_enable()
88 if (gate->enable_count == 0) in clk_enable()
94 gate->enable_count++; in clk_enable()
112 if (!gate) in clk_disable()
119 if (gate->enable_count == 0) in clk_disable()
125 if (--gate->enable_count > 0) in clk_disable()
147 if (!gate) in clk_is_enabled()
190 void put_clk_gate(struct clk_gate *gate) in put_clk_gate() argument
192 if (!gate) in put_clk_gate()
197 if (--gate->ref_count > 0) in put_clk_gate()
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| A D | drv_clock.h | 93 void put_clk_gate(struct clk_gate *gate);
94 rt_err_t clk_enable(struct clk_gate *gate);
95 rt_err_t clk_disable(struct clk_gate *gate);
96 int clk_is_enabled(struct clk_gate *gate);
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| /bsp/x86/drivers/include/ |
| A D | i386.h | 106 #define SETGATE(gate, istrap, sel, off, dpl) \ argument
108 (gate).gd_off_15_0 = (rt_uint32_t)(off)&0xffff; \
109 (gate).gd_ss = (sel); \
110 (gate).gd_args = 0; \
111 (gate).gd_rsv1 = 0; \
112 (gate).gd_type = (istrap) ? STS_TG32 : STS_IG32; \
113 (gate).gd_s = 0; \
114 (gate).gd_dpl = dpl; \
115 (gate).gd_p = 1; \
116 (gate).gd_off_31_16 = (rt_uint32_t)(off) >> 16; \
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| /bsp/allwinner/libraries/sunxi-hal/hal/source/ccmu/sunxi-ng/ |
| A D | ccu_gate.c | 9 void ccu_gate_helper_disable(struct ccu_common *common, u32 gate) in ccu_gate_helper_disable() argument
14 if (!gate) in ccu_gate_helper_disable()
22 writel(reg & ~gate, common->base + common->reg); in ccu_gate_helper_disable()
34 int ccu_gate_helper_enable(struct ccu_common *common, u32 gate) in ccu_gate_helper_enable() argument
39 if (!gate) in ccu_gate_helper_enable()
47 writel(reg | gate, common->base + common->reg); in ccu_gate_helper_enable()
61 int ccu_gate_helper_is_enabled(struct ccu_common *common, u32 gate) in ccu_gate_helper_is_enabled() argument
65 if (!gate) in ccu_gate_helper_is_enabled()
71 return !!(value & gate); in ccu_gate_helper_is_enabled()
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| A D | ccu_gate.h | 137 void ccu_gate_helper_disable(struct ccu_common *common, u32 gate);
138 int ccu_gate_helper_enable(struct ccu_common *common, u32 gate);
139 int ccu_gate_helper_is_enabled(struct ccu_common *common, u32 gate);
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| /bsp/allwinner/libraries/sunxi-hal/hal/source/prcm/prcm-sun50iw11/ |
| A D | reset.c | 129 ccu_reg_addr->r_ac_gate.gate = reset; in ccu_set_mclk_reset()
131 ccu_reg_addr->r_ac_gate.gate = reset; in ccu_set_mclk_reset()
140 ccu_reg_addr->r_dmic_gate.gate = reset; in ccu_set_mclk_reset()
142 ccu_reg_addr->r_dmic_gate.gate = reset; in ccu_set_mclk_reset()
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| A D | mclk.c | 1095 ccu_reg_addr->r_twi.gate = onoff; in ccu_set_mclk_onoff()
1099 ccu_reg_addr->r_uart.gate = onoff; in ccu_set_mclk_onoff()
1103 ccu_reg_addr->r_timer.gate = onoff; in ccu_set_mclk_onoff()
1107 ccu_reg_addr->r_twd.gate = onoff; in ccu_set_mclk_onoff()
1111 ccu_reg_addr->r_pwm.gate = onoff; in ccu_set_mclk_onoff()
1119 ccu_reg_addr->r_rtc.gate = onoff; in ccu_set_mclk_onoff()
1123 ccu_reg_addr->r_rsb.gate = onoff; in ccu_set_mclk_onoff()
1127 ccu_reg_addr->r_ir.gate = onoff; in ccu_set_mclk_onoff()
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| A D | ccu_regs.h | 54 u32 gate:1; /* bit0, gate */ member
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| /bsp/rockchip/rk3500/driver/clk/ |
| A D | clk-rk3568.c | 4421 struct rk_clk_gate *gate; in rk3568_clk_enable() local
4425 gate = &clk_gates[pdata->id]; in rk3568_clk_enable()
4426 con_regs = &cru->clkgate_con[gate->con_idx]; in rk3568_clk_enable()
4430 gate = &pmu_clk_gates[pdata->id]; in rk3568_clk_enable()
4431 con_regs = &pmucru->pmu_clkgate_con[gate->con_idx]; in rk3568_clk_enable()
4438 rk_clrreg(con_regs, RT_BIT(gate->con_bit)); in rk3568_clk_enable()
4458 struct rk_clk_gate *gate; in rk3568_clk_disable() local
4462 gate = &clk_gates[pdata->id]; in rk3568_clk_disable()
4463 con_regs = &cru->clkgate_con[gate->con_idx]; in rk3568_clk_disable()
4467 gate = &pmu_clk_gates[pdata->id]; in rk3568_clk_disable()
[all …]
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| A D | clk-rk3588.c | 2753 struct rk3588_clk_gate *gate; in rk3588_clk_enable() local
2755 gate = &clk_gates[pdata->id]; in rk3588_clk_enable()
2756 con_regs = (void*)cru + gate->offset; in rk3588_clk_enable()
2758 rk_clrreg(con_regs, RT_BIT(gate->con_bit)); in rk3588_clk_enable()
2778 struct rk3588_clk_gate *gate; in rk3588_clk_disable() local
2780 gate = &clk_gates[pdata->id]; in rk3588_clk_disable()
2781 con_regs = (void*)cru + gate->offset; in rk3588_clk_disable()
2783 rk_setreg(con_regs, RT_BIT(gate->con_bit)); in rk3588_clk_disable()
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| /bsp/nxp/lpc/lpc55sxx/docs/ |
| A D | LPC55Sxx系列BSP制作教程.md | 106 2. 配置时钟：时钟配置工具可以配置 MCU 内部的时钟线上的时钟，外设模块的 clock gate 默认是关闭的，外设初始化的时候才会被打开。如下图所示可以配置串口外设时钟频率：
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| /bsp/nxp/imx/imxrt/docs/ |
| A D | IMXRT系列BSP制作教程.md | 107 2. 配置时钟：时钟配置工具可以配置 MCU 内部的时钟线上的时钟，外设模块的 clock gate 默认是关闭的，外设初始化的时候才会被打开。如下图所示可以配置串口外设时钟频率：
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| /bsp/xuantie/libraries/xuantie_libraries/csi/csi2/include/drv/ |
| A D | tee.h | 220 int32_t csi_tee_enter_lpm(uint32_t gate, uint32_t irqid, tee_lpm_mode_e mode);
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