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Searched refs:getreg32 (Results 1 – 25 of 43) sorted by relevance

12

/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/
A Dbflb_clock.h35 volatile uint32_t regval = getreg32(BFLB_GLB_CGEN1_BASE); \
42 volatile uint32_t regval = getreg32(BFLB_GLB_CGEN1_BASE); \
49 volatile uint32_t regval = getreg32(BFLB_GLB_CGEN1_BASE); \
61 volatile uint32_t regval = getreg32(BFLB_GLB_CGEN1_BASE); \
68 volatile uint32_t regval = getreg32(BFLB_GLB_CGEN1_BASE); \
80 volatile uint32_t regval = getreg32(BFLB_GLB_CGEN1_BASE); \
87 volatile uint32_t regval = getreg32(BFLB_GLB_CGEN1_BASE); \
95 volatile uint32_t regval = getreg32(BFLB_GLB_CGEN1_BASE); \
103 volatile uint32_t regval = getreg32(BFLB_GLB_CGEN1_BASE); \
112 volatile uint32_t regval = getreg32(BFLB_GLB_CGEN1_BASE); \
[all …]
/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/
A Dbflb_uart.c17 tx_cfg = getreg32(reg_base + UART_UTX_CONFIG_OFFSET); in bflb_uart_init()
18 rx_cfg = getreg32(reg_base + UART_URX_CONFIG_OFFSET); in bflb_uart_init()
28 tx_cfg = getreg32(reg_base + UART_UTX_CONFIG_OFFSET); in bflb_uart_init()
29 rx_cfg = getreg32(reg_base + UART_URX_CONFIG_OFFSET); in bflb_uart_init()
75 regval = getreg32(reg_base + UART_URX_CONFIG_OFFSET); in bflb_uart_init()
80 regval = getreg32(reg_base + UART_SW_MODE_OFFSET); in bflb_uart_init()
84 regval = getreg32(reg_base + UART_DATA_CONFIG_OFFSET); in bflb_uart_init()
89 regval = getreg32(reg_base + UART_UTX_CONFIG_OFFSET); in bflb_uart_init()
112 tx_cfg = getreg32(reg_base + UART_UTX_CONFIG_OFFSET); in bflb_uart_init()
113 rx_cfg = getreg32(reg_base + UART_URX_CONFIG_OFFSET); in bflb_uart_init()
[all …]
A Dbflb_sec_trng.c22 regval = getreg32(reg_base + SEC_ENG_SE_TRNG_0_CTRL_0_OFFSET); in bflb_trng_read()
26 regval = getreg32(reg_base + SEC_ENG_SE_TRNG_0_CTRL_0_OFFSET); in bflb_trng_read()
43 regval = getreg32(reg_base + SEC_ENG_SE_TRNG_0_CTRL_0_OFFSET); in bflb_trng_read()
47 regval = getreg32(reg_base + SEC_ENG_SE_TRNG_0_CTRL_0_OFFSET); in bflb_trng_read()
82 regval = getreg32(reg_base + SEC_ENG_SE_TRNG_0_CTRL_0_OFFSET); in bflb_trng_read()
86 regval = getreg32(reg_base + SEC_ENG_SE_TRNG_0_CTRL_0_OFFSET); in bflb_trng_read()
90 regval = getreg32(reg_base + SEC_ENG_SE_TRNG_0_CTRL_0_OFFSET); in bflb_trng_read()
95 regval = getreg32(reg_base + SEC_ENG_SE_TRNG_0_CTRL_0_OFFSET); in bflb_trng_read()
99 regval = getreg32(reg_base + SEC_ENG_SE_TRNG_0_CTRL_0_OFFSET); in bflb_trng_read()
155 regval = getreg32(reg_base + SEC_ENG_SE_CTRL_PROT_RD_OFFSET); in bflb_group0_request_trng_access()
[all …]
A Dbflb_adc.c22 regval = getreg32(reg_base + AON_GPADC_REG_CMD_OFFSET); in bflb_adc_init()
26 regval = getreg32(reg_base + AON_GPADC_REG_CMD_OFFSET); in bflb_adc_init()
31 regval = getreg32(reg_base + AON_GPADC_REG_CMD_OFFSET); in bflb_adc_init()
44 regval = getreg32(reg_base + AON_GPADC_REG_CMD_OFFSET); in bflb_adc_init()
108 regval = getreg32(reg_base + AON_GPADC_REG_CMD_OFFSET); in bflb_adc_init()
142 regval = getreg32(reg_base + AON_GPADC_REG_ISR_OFFSET); in bflb_adc_init()
159 regval = getreg32(reg_base + AON_GPADC_REG_CMD_OFFSET); in bflb_adc_deinit()
164 regval = getreg32(reg_base + AON_GPADC_REG_CMD_OFFSET); in bflb_adc_deinit()
177 regval = getreg32(reg_base + AON_GPADC_REG_CMD_OFFSET); in bflb_adc_deinit()
262 regval = getreg32(reg_base + AON_GPADC_REG_CMD_OFFSET); in bflb_adc_start_conversion()
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A Dbflb_spi.c18 regval = getreg32(GLB_SPI_MODE_ADDRESS); in bflb_spi_init()
39 regval = getreg32(reg_base + SPI_PRD_1_OFFSET); in bflb_spi_init()
45 regval = getreg32(reg_base + SPI_CONFIG_OFFSET); in bflb_spi_init()
116 regval = getreg32(reg_base + SPI_CONFIG_OFFSET); in bflb_spi_init()
207 regval = getreg32(reg_base + SPI_CONFIG_OFFSET); in bflb_spi_poll_send()
241 regval = getreg32(reg_base + SPI_CONFIG_OFFSET); in bflb_spi_poll_exchange()
408 regval = getreg32(reg_base + SPI_INT_STS_OFFSET); in bflb_spi_txint_mask()
422 regval = getreg32(reg_base + SPI_INT_STS_OFFSET); in bflb_spi_rxint_mask()
436 regval = getreg32(reg_base + SPI_INT_STS_OFFSET); in bflb_spi_tcint_mask()
450 regval = getreg32(reg_base + SPI_INT_STS_OFFSET); in bflb_spi_errint_mask()
[all …]
A Dbflb_usb_v2.c66 regval = getreg32(BFLB_PDS_BASE + PDS_USB_CTL_OFFSET); in bflb_usb_phy_init()
73 regval = getreg32(BFLB_PDS_BASE + PDS_USB_CTL_OFFSET); in bflb_usb_phy_init()
80 regval = getreg32(BFLB_PDS_BASE + PDS_USB_CTL_OFFSET); in bflb_usb_phy_init()
97 regval = getreg32(BFLB_PDS_BASE + PDS_USB_CTL_OFFSET); in usb_hc_low_level_init()
101 regval = getreg32(BLFB_USB_BASE + USB_OTG_CSR_OFFSET); in usb_hc_low_level_init()
109 regval = getreg32(BLFB_USB_BASE + USB_OTG_CSR_OFFSET); in usb_hc_low_level_init()
413 …return (getreg32(BLFB_USB_BASE + USB_DEV_ISG0_OFFSET) & ~getreg32(BLFB_USB_BASE + USB_DEV_MISG0_OF… in bflb_usb_get_source_group_intstatus()
415 …return (getreg32(BLFB_USB_BASE + USB_DEV_ISG1_OFFSET) & ~getreg32(BLFB_USB_BASE + USB_DEV_MISG1_OF… in bflb_usb_get_source_group_intstatus()
417 …return (getreg32(BLFB_USB_BASE + USB_DEV_ISG2_OFFSET) & ~getreg32(BLFB_USB_BASE + USB_DEV_MISG2_OF… in bflb_usb_get_source_group_intstatus()
419 …return (getreg32(BLFB_USB_BASE + USB_DEV_ISG3_OFFSET) & ~getreg32(BLFB_USB_BASE + USB_DEV_MISG3_OF… in bflb_usb_get_source_group_intstatus()
[all …]
A Dbflb_dbi.c38 regval = getreg32(reg_base + DBI_CONFIG_OFFSET); in bflb_dbi_init()
109 regval = getreg32(reg_base + DBI_PIX_CNT_OFFSET); in bflb_dbi_init()
213 regval = getreg32(reg_base + DBI_CONFIG_OFFSET); in bflb_dbi_deinit()
326 regval = getreg32(reg_base + DBI_CONFIG_OFFSET); in bflb_dbi_send_cmd_data()
353 regval = getreg32(reg_base + DBI_CMD_OFFSET); in bflb_dbi_send_cmd_data()
365 regval = getreg32(reg_base + DBI_INT_STS_OFFSET); in bflb_dbi_send_cmd_data()
381 regval = getreg32(reg_base + DBI_CONFIG_OFFSET); in bflb_dbi_send_cmd_data()
410 regval = getreg32(reg_base + DBI_CONFIG_OFFSET); in bflb_dbi_send_cmd_read_data()
454 regval = getreg32(reg_base + DBI_CONFIG_OFFSET); in bflb_dbi_send_cmd_read_data()
497 regval = getreg32(reg_base + DBI_CONFIG_OFFSET); in bflb_dbi_send_cmd_pixel()
[all …]
A Dbflb_pwm_v2.c13 regval = getreg32(reg_base + PWM_MC0_CONFIG0_OFFSET); in bflb_pwm_v2_init()
19 regval = getreg32(reg_base + PWM_MC0_CONFIG0_OFFSET); in bflb_pwm_v2_init()
27 regval = getreg32(reg_base + PWM_MC0_CONFIG0_OFFSET); in bflb_pwm_v2_init()
42 regval = getreg32(reg_base + PWM_MC0_PERIOD_OFFSET); in bflb_pwm_v2_init()
56 regval = getreg32(reg_base + PWM_MC0_CONFIG0_OFFSET); in bflb_pwm_v2_deinit()
105 regval = getreg32(reg_base + PWM_MC0_PERIOD_OFFSET); in bflb_pwm_v2_set_period()
118 regval = getreg32(reg_base + PWM_MC0_CONFIG0_OFFSET); in bflb_pwm_v2_start()
139 regval = getreg32(reg_base + PWM_MC0_CONFIG0_OFFSET); in bflb_pwm_v2_stop()
161 regval = getreg32(reg_base + PWM_MC0_CONFIG0_OFFSET); in bflb_pwm_v2_get_frequency()
182 regval = getreg32(reg_base + PWM_MC0_PERIOD_OFFSET); in bflb_pwm_v2_get_frequency()
[all …]
A Dbflb_audac.c19 regval = getreg32(reg_base + AUDAC_0_OFFSET); in bflb_audac_init()
33 regval = getreg32(reg_base + AUDAC_1_OFFSET); in bflb_audac_init()
47 regval = getreg32(reg_base + AUDAC_FIFO_CTRL_OFFSET); in bflb_audac_init()
74 regval = getreg32(reg_base + AUDAC_ZD_0_OFFSET); in bflb_audac_init()
81 regval = getreg32(reg_base + AUDAC_STATUS_OFFSET); in bflb_audac_init()
130 regval = getreg32(reg_base + AUDAC_S0_OFFSET); in bflb_audac_volume_init()
170 regval = getreg32(reg_base + AUDAC_FIFO_CTRL_OFFSET); in bflb_audac_link_rxdma()
190 regval = getreg32(reg_base + AUDAC_0_OFFSET); in bflb_audac_int_mask()
216 regval = getreg32(reg_base + AUDAC_0_OFFSET); in bflb_audac_int_unmask()
243 regval = getreg32(reg_base + AUDAC_0_OFFSET); in bflb_audac_get_intstatus()
[all …]
A Dbflb_pwm_v1.c13 regval = getreg32(reg_base + PWM0_CONFIG_OFFSET + ch * 0x20); in bflb_pwm_v1_channel_init()
19 regval = getreg32(reg_base + PWM0_CONFIG_OFFSET + ch * 0x20); in bflb_pwm_v1_channel_init()
27 regval = getreg32(reg_base + PWM0_CONFIG_OFFSET + ch * 0x20); in bflb_pwm_v1_channel_init()
39 regval = getreg32(reg_base + PWM0_CLKDIV_OFFSET + ch * 0x20); in bflb_pwm_v1_channel_init()
45 regval = getreg32(reg_base + PWM0_PERIOD_OFFSET + ch * 0x20); in bflb_pwm_v1_channel_init()
59 regval = getreg32(reg_base + PWM0_CONFIG_OFFSET + ch * 0x20); in bflb_pwm_v1_channel_deinit()
103 regval = getreg32(reg_base + PWM0_CONFIG_OFFSET + ch * 0x20); in bflb_pwm_v1_start()
159 regval = getreg32(reg_base + PWM0_THRE1_OFFSET + ch * 0x20); in bflb_pwm_v1_channel_set_threshold()
192 regval = getreg32(reg_base + PWM_INT_CONFIG_OFFSET); in bflb_pwm_v1_get_intstatus()
203 regval = getreg32(reg_base + PWM_INT_CONFIG_OFFSET); in bflb_pwm_v1_int_clear()
[all …]
A Dbflb_emac.c96 bd = getreg32(reg_base + EMAC_TX_BD_NUM_OFFSET); in bflb_emac_bd_get_cur_active()
344 reg_val = getreg32(GLB_EMAC_CLK_OUT_ADDRESS); in bflb_emac_init()
358 reg_val = getreg32(GLB_UNGATE_CFG2_ADDRESS); in bflb_emac_init()
371 reg_val = getreg32(GLB_CLOCK_CFG3_ADDRESS); in bflb_emac_init()
380 reg_val = getreg32(GLB_UNGATE_CFG1_ADDRESS); in bflb_emac_init()
387 reg_val = getreg32(reg_base + EMAC_MODE_OFFSET); in bflb_emac_init()
400 reg_val = getreg32(reg_base + EMAC_IPGT_OFFSET); in bflb_emac_init()
406 reg_val = getreg32(reg_base + EMAC_MIIMODE_OFFSET); in bflb_emac_init()
420 reg_val = getreg32(reg_base + EMAC_PACKETLEN_OFFSET); in bflb_emac_init()
427 reg_val = getreg32(reg_base + EMAC_MAC_ADDR0_OFFSET); in bflb_emac_init()
[all …]
A Dbflb_dac.c18 regval = getreg32(reg_base + GLB_GPDAC_CTRL_OFFSET); in bflb_dac_init()
27 regval = getreg32(reg_base + GLB_GPDAC_CTRL_OFFSET); in bflb_dac_init()
36 regval = getreg32(reg_base + GLB_GPDAC_CTRL_OFFSET); in bflb_dac_init()
40 regval = getreg32(reg_base + GLB_GPDAC_CTRL_OFFSET); in bflb_dac_init()
65 regval = getreg32(reg_base + GLB_GPDAC_ACTRL_OFFSET); in bflb_dac_channel_enable()
71 regval = getreg32(reg_base + GLB_GPDAC_BCTRL_OFFSET); in bflb_dac_channel_enable()
75 regval = getreg32(reg_base + GLB_GPDAC_ACTRL_OFFSET); in bflb_dac_channel_enable()
90 regval = getreg32(reg_base + GLB_GPDAC_ACTRL_OFFSET); in bflb_dac_channel_disable()
96 regval = getreg32(reg_base + GLB_GPDAC_BCTRL_OFFSET); in bflb_dac_channel_disable()
111 regval1 = getreg32(DAC_GPIP_BASE + GPIP_GPDAC_CONFIG_OFFSET); in bflb_dac_link_txdma()
[all …]
A Dbflb_i2s.c13 regval = getreg32(reg_base + I2S_CONFIG_OFFSET); in bflb_i2s_init()
82 regval = getreg32(reg_base + I2S_BCLK_CONFIG_OFFSET); in bflb_i2s_init()
90 regval = getreg32(reg_base + I2S_FIFO_CONFIG_1_OFFSET); in bflb_i2s_init()
97 regval = getreg32(reg_base + I2S_FIFO_CONFIG_0_OFFSET); in bflb_i2s_init()
112 regval = getreg32(reg_base + I2S_IO_CONFIG_OFFSET); in bflb_i2s_init()
123 regval = getreg32(reg_base + I2S_CONFIG_OFFSET); in bflb_i2s_init()
140 regval = getreg32(reg_base + I2S_CONFIG_OFFSET); in bflb_i2s_deinit()
152 regval = getreg32(reg_base + I2S_FIFO_CONFIG_0_OFFSET); in bflb_i2s_link_txdma()
181 regval = getreg32(reg_base + I2S_INT_STS_OFFSET); in bflb_i2s_txint_mask()
195 regval = getreg32(reg_base + I2S_INT_STS_OFFSET); in bflb_i2s_rxint_mask()
[all …]
A Dbflb_sec_sha.c37 regval = getreg32(reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET); in bflb_sha_init()
54 regval = getreg32(reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET); in bflb_sha1_start()
75 regval = getreg32(reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET); in bflb_sha512_start()
95 regval = getreg32(reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET); in bflb_sha1_update()
142 regval = getreg32(reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET); in bflb_sha1_update()
202 regval = getreg32(reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET); in bflb_sha512_update()
248 regval = getreg32(reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET); in bflb_sha512_update()
365 regval = getreg32(reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET); in bflb_sha1_finish()
495 regval = getreg32(reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET); in bflb_sha512_finish()
508 regval = getreg32(reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET); in bflb_sha_link_init()
[all …]
A Dbflb_auadc.c11 regval = getreg32(reg_base + AUADC_AUDPDM_TOP_OFFSET); in bflb_auadc_init()
20 regval = getreg32(reg_base + AUADC_AUDPDM_ITF_OFFSET); in bflb_auadc_init()
26 regval = getreg32(reg_base + AUADC_PDM_DAC_0_OFFSET); in bflb_auadc_init()
35 regval = getreg32(reg_base + AUADC_PDM_PDM_0_OFFSET); in bflb_auadc_init()
52 regval = getreg32(reg_base + AUADC_AUDADC_CMD_OFFSET); in bflb_auadc_init()
64 regval = getreg32(reg_base + AUADC_AUDADC_RX_FIFO_CTRL_OFFSET); in bflb_auadc_init()
92 regval = getreg32(reg_base + AUADC_AUDPDM_ITF_OFFSET); in bflb_auadc_init()
108 regval = getreg32(reg_base + AUADC_AUDADC_CMD_OFFSET); in bflb_auadc_adc_init()
117 regval = getreg32(reg_base + AUADC_AUDADC_CMD_OFFSET); in bflb_auadc_adc_init()
262 regval = getreg32(reg_base + AUADC_PDM_ADC_S0_OFFSET); in bflb_auadc_feature_control()
[all …]
A Dbflb_gpio.c39 cfg = getreg32(cfg_address); in bflb_gpio_init()
218 regval = getreg32(cfg_address); in bflb_gpio_int_init()
223 regval = getreg32(cfg_address); in bflb_gpio_int_init()
228 regval = getreg32(cfg_address); in bflb_gpio_int_init()
245 regval = getreg32(cfg_address); in bflb_gpio_int_mask()
254 regval = getreg32(cfg_address); in bflb_gpio_int_mask()
283 regval = getreg32(cfg_address); in bflb_gpio_int_clear()
291 regval = getreg32(cfg_address); in bflb_gpio_int_clear()
309 regval = getreg32(reg_base + GLB_UART_SIG_SEL_0_OFFSET); in bflb_gpio_uart_init()
356 regval = getreg32(reg_base + GLB_UART_CFG1_OFFSET); in bflb_gpio_uart_init()
[all …]
A Dbflb_ir.c111 regval = getreg32(reg_base + IRTX_CONFIG_OFFSET); in bflb_ir_tx_init()
209 regval = getreg32(reg_base + IRTX_CONFIG_OFFSET); in bflb_ir_send()
301 regval = getreg32(reg_base + IRTX_CONFIG_OFFSET); in bflb_ir_swm_send()
338 regval = getreg32(reg_base + IRTX_CONFIG_OFFSET); in bflb_ir_swm_send()
351 regval = getreg32(reg_base + IRTX_CONFIG_OFFSET); in bflb_ir_tx_enable()
446 regval = getreg32(reg_base + IRRX_CONFIG_OFFSET); in bflb_ir_rx_init()
493 regval = getreg32(reg_base + IRRX_CONFIG_OFFSET); in bflb_ir_receive()
510 …*data = getreg32(reg_base + IRRX_DATA_WORD0_OFFSET) | (uint64_t)getreg32(reg_base + IRRX_DATA_WORD… in bflb_ir_receive()
525 regval = getreg32(reg_base + IRRX_CONFIG_OFFSET); in bflb_ir_swm_receive()
540 regval = getreg32(reg_base + IRRX_CONFIG_OFFSET); in bflb_ir_swm_receive()
[all …]
A Dbflb_cam.c50 regval = getreg32(reg_base + CAM_DVP2AXI_HSYNC_CROP_OFFSET); in bflb_cam_init()
64 regval = getreg32(reg_base + CAM_DVP2AXI_VSYNC_CROP_OFFSET); in bflb_cam_init()
85 regval = getreg32(CAM_FRONT_BASE + CAM_FRONT_CONFIG_OFFSET); in bflb_cam_init()
96 regval = getreg32(reg_base + CAM_DVP2AXI_CONFIGUE_OFFSET); in bflb_cam_init()
299 regval = getreg32(reg_base + CAM_DVP2AXI_CONFIGUE_OFFSET); in bflb_cam_init()
381 regval = getreg32(CAM_FRONT_BASE + CAM_FRONT_CONFIG_OFFSET); in bflb_cam_init()
394 regval = getreg32(reg_base + CAM_DVP2AXI_CONFIGUE_OFFSET); in bflb_cam_start()
405 regval = getreg32(reg_base + CAM_DVP2AXI_CONFIGUE_OFFSET); in bflb_cam_stop()
417 regval = getreg32(reg_base + CAM_INT_CONTROL_OFFSET); in bflb_cam_int_mask()
469 regval = getreg32(CAM_FRONT_BASE + CAM_FRONT_CONFIG_OFFSET); in bflb_cam_swap_input_yu_order()
[all …]
A Dbflb_timer.c13 regval = getreg32(reg_base + TIMER_TCER_OFFSET); in bflb_timer_init()
23 regval = getreg32(reg_base + TIMER_TCCR_OFFSET); in bflb_timer_init()
34 regval = getreg32(reg_base + TIMER_TCDR_OFFSET); in bflb_timer_init()
40 regval = getreg32(reg_base + TIMER_TCMR_OFFSET); in bflb_timer_init()
98 regval = getreg32(reg_base + TIMER_TCER_OFFSET); in bflb_timer_deinit()
110 regval = getreg32(reg_base + TIMER_TCER_OFFSET); in bflb_timer_start()
122 regval = getreg32(reg_base + TIMER_TCER_OFFSET); in bflb_timer_stop()
212 regval = getreg32(0x20000000 + 0xc); in bflb_timer_capture_init()
239 regval = getreg32(0x20000000 + 0x258); in bflb_timer_capture_init()
267 regval = getreg32(reg_base + TIMER_GPIO_OFFSET); in bflb_timer_capture_init()
[all …]
A Dbflb_kys.c55 reg_val = getreg32(reg_base + KYS_KS_CTRL_OFFSET); in bflb_kys_init()
60 reg_val = getreg32(reg_base + KYS_KS_INT_EN_OFFSET); in bflb_kys_init()
73 reg_val = getreg32(reg_base + KYS_KS_CTRL_OFFSET); in bflb_kys_init()
106 reg_val = getreg32(reg_base + KYS_KS_CTRL_OFFSET); in bflb_kys_enable()
122 reg_val = getreg32(reg_base + KYS_KS_CTRL_OFFSET); in bflb_kys_disable()
140 reg_val_en = getreg32(reg_base + KYS_KS_INT_EN_OFFSET); in bflb_kys_int_enable()
172 reg_sts_val = getreg32(reg_base + KYS_KS_INT_STS_OFFSET); in bflb_kys_get_int_status()
173 reg_mask_val = getreg32(reg_base + KYS_KS_INT_EN_OFFSET); in bflb_kys_get_int_status()
194 reg_val = getreg32(reg_base + KYS_KEYFIFO_IDX_OFFSET); in bflb_kys_get_fifo_info()
212 return (uint8_t)(getreg32(dev->reg_base + KYS_KEYFIFO_VALUE_OFFSET) & 0xff); in bflb_kys_read_keyvalue()
[all …]
A Dbflb_rtc.c20 regval = getreg32(reg_base + HBN_CTL_OFFSET); in bflb_rtc_disable()
34 regval = getreg32(reg_base + HBN_CTL_OFFSET); in bflb_rtc_set_time()
43 regval = getreg32(reg_base + HBN_RTC_TIME_H_OFFSET); in bflb_rtc_set_time()
50 rtc_cnt = getreg32(reg_base + HBN_RTC_TIME_H_OFFSET) & 0xff; in bflb_rtc_set_time()
52 rtc_cnt |= getreg32(reg_base + HBN_RTC_TIME_L_OFFSET); in bflb_rtc_set_time()
62 regval = getreg32(reg_base + HBN_CTL_OFFSET); in bflb_rtc_set_time()
77 regval = getreg32(reg_base + HBN_RTC_TIME_H_OFFSET); in bflb_rtc_get_time()
84 time_l = getreg32(reg_base + HBN_RTC_TIME_L_OFFSET); in bflb_rtc_get_time()
85 time_h = getreg32(reg_base + HBN_RTC_TIME_H_OFFSET) & 0xff; in bflb_rtc_get_time()
A Dbflb_mjpeg.c11 regval = getreg32(reg_base + MJPEG_HEADER_BYTE_OFFSET); in bflb_mjpeg_set_yuv422_interleave_order()
46 regval = getreg32(reg_base + MJPEG_CONTROL_1_OFFSET); in bflb_mjpeg_init()
124 regval = getreg32(reg_base + MJPEG_CONTROL_2_OFFSET); in bflb_mjpeg_init()
130 regval = getreg32(reg_base + MJPEG_SWAP_MODE_OFFSET); in bflb_mjpeg_init()
165 regval = getreg32(reg_base + MJPEG_CONTROL_3_OFFSET); in bflb_mjpeg_init()
230 regval = getreg32(reg_base + MJPEG_CONTROL_1_OFFSET); in bflb_mjpeg_start()
242 regval = getreg32(reg_base + MJPEG_CONTROL_1_OFFSET); in bflb_mjpeg_stop()
254 regval = getreg32(reg_base + MJPEG_CONTROL_2_OFFSET); in bflb_mjpeg_sw_run()
261 regval = getreg32(reg_base + MJPEG_CONTROL_2_OFFSET); in bflb_mjpeg_sw_run()
265 regval = getreg32(reg_base + MJPEG_CONTROL_2_OFFSET); in bflb_mjpeg_sw_run()
[all …]
A Dbflb_dma.c28 regval = getreg32(dma_base[0] + DMA_INTTCSTATUS_OFFSET); in dma0_isr()
43 regval = getreg32(dma_base[1] + DMA_INTTCSTATUS_OFFSET); in dma1_isr()
57 regval = getreg32(dma_base[2] + DMA_INTTCSTATUS_OFFSET); in dma2_isr()
81 regval = getreg32(channel_base + DMA_CxCONFIG_OFFSET); in bflb_dma_channel_init()
88 regval = getreg32(channel_base + DMA_CxCONTROL_OFFSET); in bflb_dma_channel_init()
105 regval = getreg32(channel_base + DMA_CxCONFIG_OFFSET); in bflb_dma_channel_init()
116 regval = getreg32(channel_base + DMA_CxCONFIG_OFFSET); in bflb_dma_channel_init()
120 regval = getreg32(channel_base + DMA_CxCONTROL_OFFSET); in bflb_dma_channel_init()
301 regval = getreg32(channel_base + DMA_CxCONFIG_OFFSET); in bflb_dma_channel_start()
314 regval = getreg32(channel_base + DMA_CxCONFIG_OFFSET); in bflb_dma_channel_stop()
[all …]
A Dbflb_i2c.c20 regval = getreg32(reg_base + I2C_CONFIG_OFFSET); in bflb_i2c_addr_config()
51 regval = getreg32(reg_base + I2C_CONFIG_OFFSET); in bflb_i2c_set_dir()
68 regval = getreg32(reg_base + I2C_CONFIG_OFFSET); in bflb_i2c_set_datalen()
113 regval = getreg32(reg_base + I2C_BUS_BUSY_OFFSET); in bflb_i2c_isbusy()
129 regval = getreg32(reg_base + I2C_INT_STS_OFFSET); in bflb_i2c_isend()
145 regval = getreg32(reg_base + I2C_INT_STS_OFFSET); in bflb_i2c_isnak()
161 regval = getreg32(reg_base + I2C_CONFIG_OFFSET); in bflb_i2c_enable()
173 regval = getreg32(reg_base + I2C_CONFIG_OFFSET); in bflb_i2c_disable()
182 regval = getreg32(reg_base + I2C_INT_STS_OFFSET); in bflb_i2c_disable()
196 regval = getreg32(reg_base + I2C_CONFIG_OFFSET); in bflb_i2c_isenable()
[all …]
/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/flash/
A Dbflb_sf_ctrl.c144 regval = getreg32(reg_base + SF_CTRL_0_OFFSET); in bflb_sf_ctrl_enable()
181 regval = getreg32(reg_base + SF_CTRL_1_OFFSET); in bflb_sf_ctrl_enable()
524 regval = getreg32(reg_base + SF_CTRL_2_OFFSET); in bflb_sf_ctrl_remap_set()
529 regval = getreg32(reg_base + SF_CTRL_2_OFFSET); in bflb_sf_ctrl_remap_set()
556 regval = getreg32(reg_base + SF_CTRL_0_OFFSET); in bflb_sf_ctrl_32bits_addr_en()
585 regval = getreg32(reg_base + SF_CTRL_2_OFFSET); in bflb_sf_ctrl_psram_init()
621 regval = getreg32(reg_base + SF_CTRL_1_OFFSET); in bflb_sf_ctrl_psram_init()
646 regval = getreg32(reg_base + SF_CTRL_0_OFFSET); in bflb_sf_ctrl_get_clock_delay()
670 regval = getreg32(reg_base + SF_CTRL_0_OFFSET); in bflb_sf_ctrl_set_clock_delay()
697 regval = getreg32(reg_base + SF_CTRL_3_OFFSET); in bflb_sf_ctrl_get_wrap_queue_value()
[all …]

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