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Searched refs:gpio_num (Results 1 – 10 of 10) sorted by relevance

/bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/source/
A Dhal_gpio.c124 hal_set_gpio(gpio_num); in hal_write_gpio()
126 hal_clr_gpio(gpio_num); in hal_write_gpio()
130 void hal_set_gpio(uint8_t gpio_num) { in hal_set_gpio() argument
133 papbgpio->setgpio_b.gpio_num = gpio_num; in hal_set_gpio()
136 void hal_clr_gpio(uint8_t gpio_num) { in hal_clr_gpio() argument
139 papbgpio->clrgpio_b.gpio_num = gpio_num; in hal_clr_gpio()
145 papbgpio->toggpio_b.gpio_num = gpio_num; in hal_toggle_gpio()
152 while ((value & 0xff) != gpio_num) { in hal_set_gpio_num()
180 papbgpio->setsel_b.gpio_num = gpio_num; // Set address for following reads in hal_read_gpio_status_raw()
189 papbgpio->intack = gpio_num; in hal_gpio_int_ack()
[all …]
/bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/include/
A Dhal_gpio.h37 void hal_write_gpio(uint8_t gpio_num, uint8_t value);
38 void hal_set_gpio(uint8_t gpio_num);
39 void hal_clr_gpio(uint8_t gpio_num);
40 void hal_toggle_gpio(uint8_t gpio_num);
42 void hal_set_gpio_num(uint8_t gpio_num);
45 void hal_set_gpio_mode(uint8_t gpio_num, uint8_t gpio_mode);
47 void hal_enable_gpio_interrupt(uint8_t gpio_num);
48 void hal_disable_gpio_interrupt(uint8_t gpio_num);
50 void hal_efpgaio_output(uint8_t gpio_num, efpgaio_enum_typedef value);
51 void hal_efpgaio_outen(uint8_t gpio_num, efpgaio_enum_typedef value);
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A Dhal_apb_gpio_reg_defs.h50 __IO uint32_t gpio_num : 8; member
58 __IO uint32_t gpio_num : 8; member
66 __IO uint32_t gpio_num : 8; member
139 __IO uint32_t gpio_num : 8; member
163 __IO uint32_t gpio_num : 8; member
173 __IO uint32_t gpio_num : 8; member
182 __IO uint32_t gpio_num : 8; member
/bsp/allwinner/libraries/sunxi-hal/hal/source/sdmmc/
A Dhal_sdpin.c65 int gpio_num = 0; in sdmmc_pinctl_set_from_cfg() local
84 gpio_num = (gpiocfg[i].port - 1) * PINS_PER_BANK + gpiocfg[i].port_num; in sdmmc_pinctl_set_from_cfg()
85 ret = hal_gpio_pinmux_set_function(gpio_num, gpiocfg[i].mul_sel); in sdmmc_pinctl_set_from_cfg()
89 sdc_str, gpio_num, ret); in sdmmc_pinctl_set_from_cfg()
93 ret = hal_gpio_set_driving_level(gpio_num, gpiocfg[i].drv_level); in sdmmc_pinctl_set_from_cfg()
97 sdc_str, gpio_num, ret); in sdmmc_pinctl_set_from_cfg()
100 ret = hal_gpio_set_pull(gpio_num, gpiocfg[i].pull); in sdmmc_pinctl_set_from_cfg()
104 sdc_str, gpio_num, ret); in sdmmc_pinctl_set_from_cfg()
/bsp/ESP32_C3/drivers/
A Ddrv_pwm.c105 ledc_channel.gpio_num = BSP_LEDC_CH0_GPIO; in pwm_enabled()
108 ledc_channel.gpio_num = BSP_LEDC_CH1_GPIO; in pwm_enabled()
111 ledc_channel.gpio_num = BSP_LEDC_CH2_GPIO; in pwm_enabled()
114 ledc_channel.gpio_num = BSP_LEDC_CH3_GPIO; in pwm_enabled()
117 ledc_channel.gpio_num = BSP_LEDC_CH4_GPIO; in pwm_enabled()
120 ledc_channel.gpio_num = BSP_LEDC_CH5_GPIO; in pwm_enabled()
/bsp/allwinner/libraries/sunxi-hal/hal/source/spi/platform/
A Dspi_sun8iw19.h45 {.reg_base = SUNXI_SPI0_PBASE, .irq_num = SUNXI_IRQ_SPI0, .gpio_num = 6, \
50 {.reg_base = SUNXI_SPI1_PBASE, .irq_num = SUNXI_IRQ_SPI1, .gpio_num = 4, \
55 {.reg_base = SUNXI_SPI2_PBASE, .irq_num = SUNXI_IRQ_SPI2, .gpio_num = 4, \
A Dspi_sun8iw18.h43 {.reg_base = SUNXI_SPI0_PBASE, .irq_num = SUNXI_IRQ_SPI0, .gpio_num = 6, \
48 {.reg_base = SUNXI_SPI1_PBASE, .irq_num = SUNXI_IRQ_SPI1, .gpio_num = 4, \
A Dspi_sun8iw20.h43 {.reg_base = SUNXI_SPI0_PBASE, .irq_num = SUNXI_IRQ_SPI0, .gpio_num = 6, \
48 {.reg_base = SUNXI_SPI1_PBASE, .irq_num = SUNXI_IRQ_SPI1, .gpio_num = 4, \
/bsp/allwinner/libraries/sunxi-hal/hal/source/spi/
A Dplatform_spi.h39 uint8_t gpio_num; member
/bsp/samd21/sam_d2x_asflib/sam0/drivers/spi/
A Dspi.c856 uint8_t gpio_num = slave->ss_pin; in spi_select_slave() local
859 gpio_pin_set_output_level(gpio_num, false); in spi_select_slave()
862 gpio_pin_set_output_level(gpio_num, true); in spi_select_slave()

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