1 /* 2 * Copyright (C) 2019 ETH Zurich, University of Bologna 3 * and GreenWaves Technologies 4 * 5 * Licensed under the Apache License, Version 2.0 (the "License"); 6 * you may not use this file except in compliance with the License. 7 * You may obtain a copy of the License at 8 * 9 * http://www.apache.org/licenses/LICENSE-2.0 10 * 11 * Unless required by applicable law or agreed to in writing, software 12 * distributed under the License is distributed on an "AS IS" BASIS, 13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 * See the License for the specific language governing permissions and 15 * limitations under the License. 16 */ 17 18 #ifndef HAL_INCLUDE_HAL_GPIO_PERIPH_H_ 19 #define HAL_INCLUDE_HAL_GPIO_PERIPH_H_ 20 21 22 /* ---------------------------------------------------------------------------- 23 -- GPIO Peripheral Access Layer -- 24 ---------------------------------------------------------------------------- */ 25 26 /** GPIO_Type Register Layout Typedef */ 27 typedef struct 28 { 29 volatile uint32_t paddir; /**< GPIO pad direction configuration register. */ 30 volatile uint32_t gpioen; /**< GPIO pad enable configuration register. */ 31 volatile uint32_t padin; /**< GPIO pad input value register. */ 32 volatile uint32_t padout; /**< GPIO pad output value register. */ 33 volatile uint32_t padoutset; /**< GPIO pad output set register. */ 34 volatile uint32_t padoutclr; /**< GPIO pad output clear register. */ 35 volatile uint32_t inten; /**< GPIO pad interrupt enable configuration register. */ 36 volatile uint32_t inttype[2]; /**< GPIO pad interrupt type bit 0 & 1 configuration register. */ 37 volatile uint32_t intstatus; /**< GPIO pad interrupt status register. */ 38 volatile uint32_t padcfg[4]; /**< GPIO pad pin configuration register : 0-7, 8-15, 16-23, 23-31. */ 39 } gpio_t; 40 41 42 /* ---------------------------------------------------------------------------- 43 -- GPIO Register Bitfield Access -- 44 ---------------------------------------------------------------------------- */ 45 46 /*! @name PADDIR */ 47 /* GPIO direction configuration bitfield: 48 - bit[i]=1'b0: Input mode for GPIO[i] 49 - bit[i]=1'b1: Output mode for GPIO[i] */ 50 #define GPIO_PADDIR_DIR_MASK (0xffffffff) 51 #define GPIO_PADDIR_DIR_SHIFT (0) 52 #define GPIO_PADDIR_DIR(val) (((uint32_t)(((uint32_t)(val)) << GPIO_PADDIR_DIR_SHIFT)) & GPIO_PADDIR_DIR_MASK) 53 54 55 /*! @name GPIOEN */ 56 /* GPIO clock enable configuration bitfield: 57 - bit[i]=1'b0: disable clock for GPIO[i] 58 - bit[i]=1'b1: enable clock for GPIO[i] 59 GPIOs are gathered by groups of 4. The clock gating of one group is done only if all 4 GPIOs are disabled. 60 Clock must be enabled for a GPIO if it's direction is configured in input mode. */ 61 #define GPIO_GPIOEN_GPIOEN_MASK (0xffffffff) 62 #define GPIO_GPIOEN_GPIOEN_SHIFT (0) 63 #define GPIO_GPIOEN_GPIOEN(val) (((uint32_t)(((uint32_t)(val)) << GPIO_GPIOEN_GPIOEN_SHIFT)) & GPIO_GPIOEN_GPIOEN_MASK) 64 65 66 /*! @name PADIN */ 67 /* GPIO input data read bitfield. DATA_IN[i] corresponds to input data of GPIO[i]. */ 68 #define GPIO_PADIN_DATA_IN_MASK (0xffffffff) 69 #define GPIO_PADIN_DATA_IN_SHIFT (0) 70 #define GPIO_PADIN_DATA_IN(val) (((uint32_t)(((uint32_t)(val)) << GPIO_PADIN_DATA_IN_SHIFT)) & GPIO_PADIN_DATA_IN_MASK) 71 72 73 /*! @name PADOUT */ 74 /* GPIO output data read bitfield. DATA_OUT[i] corresponds to output data set on GPIO[i]. */ 75 #define GPIO_PADOUT_DATA_OUT_MASK (0xffffffff) 76 #define GPIO_PADOUT_DATA_OUT_SHIFT (0) 77 #define GPIO_PADOUT_DATA_OUT(val) (((uint32_t)(((uint32_t)(val)) << GPIO_PADOUT_DATA_OUT_SHIFT)) & GPIO_PADOUT_DATA_OUT_MASK) 78 79 80 /*! @name PADOUTSET */ 81 /* GPIO output data read bitfield. DATA_OUT[i] corresponds to output data set on GPIO[i]. */ 82 #define GPIO_PADOUTSET_DATA_OUT_MASK (0xffffffff) 83 #define GPIO_PADOUTSET_DATA_OUT_SHIFT (0) 84 #define GPIO_PADOUTSET_DATA_OUT(val) (((uint32_t)(((uint32_t)(val)) << GPIO_PADOUTSET_DATA_OUT_SHIFT)) & GPIO_PADOUTSET_DATA_OUT_MASK) 85 86 87 /*! @name PADOUTCLEAR */ 88 /* GPIO output data read bitfield. DATA_OUT[i] corresponds to output data set on GPIO[i]. */ 89 #define GPIO_PADOUTCLR_DATA_OUT_MASK (0xffffffff) 90 #define GPIO_PADOUTCLR_DATA_OUT_SHIFT (0) 91 #define GPIO_PADOUTCLR_DATA_OUT(val) (((uint32_t)(((uint32_t)(val)) << GPIO_PADOUTCLR_DATA_OUT_SHIFT)) & GPIO_PADOUTCLR_DATA_OUT_MASK) 92 93 94 /*! @name INTEN */ 95 /* GPIO interrupt enable configuration bitfield: 96 - bit[i]=1'b0: disable interrupt for GPIO[i] 97 - bit[i]=1'b1: enable interrupt for GPIO[i] */ 98 #define GPIO_INTEN_INTEN_MASK (0xffffffff) 99 #define GPIO_INTEN_INTEN_SHIFT (0) 100 #define GPIO_INTEN_INTEN(val) (((uint32_t)(((uint32_t)(val)) << GPIO_INTEN_INTEN_SHIFT)) & GPIO_INTEN_INTEN_MASK) 101 102 103 /*! @name INTTYPE0 */ 104 /* GPIO[15:0] interrupt type configuration bitfield: 105 - bit[2*i+1:2*i]=2'b00: interrupt on falling edge for GPIO[i] 106 - bit[2*i+1:2*i]=2'b01: interrupt on rising edge for GPIO[i] 107 - bit[2*i+1:2*i]=2'b10: interrupt on rising and falling edge for GPIO[i] 108 - bit[2*i+1:2*i]=2'b11: RFU */ 109 #define GPIO_INTTYPE_INTTYPE_MASK (0xffffffff) 110 #define GPIO_INTTYPE_INTTYPE_SHIFT (0) 111 #define GPIO_INTTYPE_INTTYPE(val) (((uint32_t)(((uint32_t)(val)) << GPIO_INTTYPE_INTTYPE_SHIFT)) & GPIO_INTTYPE_INTTYPE_MASK) 112 113 114 /*! @name INTSTATUS */ 115 /* GPIO Interrupt status flags bitfield. INTSTATUS[i]=1 when interrupt received on GPIO[i]. INTSTATUS is cleared when it is red. GPIO interrupt line is also cleared when INTSTATUS register is red. */ 116 #define GPIO_INTSTATUS_INTSTATUS_MASK (0xffffffff) 117 #define GPIO_INTSTATUS_INTSTATUS_SHIFT (0) 118 #define GPIO_INTSTATUS_INTSTATUS(val) (((uint32_t)(((uint32_t)(val)) << GPIO_INTSTATUS_INTSTATUS_SHIFT)) & GPIO_INTSTATUS_INTSTATUS_MASK) 119 120 121 /*! @name PADCFG */ 122 /* GPIO[i] pull activation configuration bitfield: 123 - 1'b0: pull disabled 124 - 1'b1: pull enabled */ 125 #define GPIO_PADCFG_GPIO_PE_MASK (0x1) 126 #define GPIO_PADCFG_GPIO_PE_SHIFT (0) 127 #define GPIO_PADCFG_GPIO_PE(val) (((uint32_t)(((uint32_t)(val)) << GPIO_PADCFG_GPIO_PE_SHIFT)) & GPIO_PADCFG_GPIO_PE_MASK) 128 129 130 /* GPIO[i] drive strength configuration bitfield: 131 - 1'b0: low drive strength 132 - 1'b1: high drive strength */ 133 #define GPIO_PADCFG_GPIO_DS_MASK (0x2) 134 #define GPIO_PADCFG_GPIO_DS_SHIFT (1) 135 #define GPIO_PADCFG_GPIO_DS(val) (((uint32_t)(((uint32_t)(val)) << GPIO_PADCFG_GPIO_DS_SHIFT)) & GPIO_PADCFG_GPIO_DS_MASK) 136 137 138 /*! @name PADDIR */ 139 typedef union 140 { 141 struct 142 { 143 /* GPIO direction configuration bitfield: 144 - bit[i]=1'b0: Input mode for GPIO[i] 145 - bit[i]=1'b1: Output mode for GPIO[i] */ 146 uint32_t dir:32; 147 } field; 148 uint32_t word; 149 } gpio_paddir_t; 150 151 /*! @name PADIN */ 152 typedef union 153 { 154 struct 155 { 156 /* GPIO input data read bitfield. DATA_IN[i] corresponds to input data of GPIO[i]. */ 157 uint32_t data_in:32; 158 } field; 159 uint32_t word; 160 } gpio_padin_t; 161 162 /*! @name PADOUT */ 163 typedef union 164 { 165 struct 166 { 167 /* GPIO output data read bitfield. DATA_OUT[i] corresponds to output data set on GPIO[i]. */ 168 uint32_t data_out:32; 169 } field; 170 uint32_t word; 171 } gpio_padout_t; 172 173 /*! @name INTEN */ 174 typedef union 175 { 176 struct 177 { 178 /* GPIO interrupt enable configuration bitfield: 179 - bit[i]=1'b0: disable interrupt for GPIO[i] 180 - bit[i]=1'b1: enable interrupt for GPIO[i] */ 181 uint32_t inten:32; 182 } field; 183 uint32_t word; 184 } gpio_inten_t; 185 186 /*! @name INTTYPE */ 187 typedef union 188 { 189 struct 190 { 191 /* GPIO[15:0] interrupt type configuration bitfield: 192 - bit[2*i+1:2*i]=2'b00: interrupt on falling edge for GPIO[i] 193 - bit[2*i+1:2*i]=2'b01: interrupt on rising edge for GPIO[i] 194 - bit[2*i+1:2*i]=2'b10: interrupt on rising and falling edge for GPIO[i] 195 - bit[2*i+1:2*i]=2'b11: RFU */ 196 uint32_t inttype:32; 197 } field; 198 uint32_t word; 199 } gpio_inttype0_t; 200 201 /*! @name INTSTATUS */ 202 typedef union 203 { 204 struct 205 { 206 /* GPIO Interrupt status flags bitfield. INTSTATUS[i]=1 when interrupt received on GPIO[i]. INTSTATUS is cleared when it is red. GPIO interrupt line is also cleared when INTSTATUS register is red. */ 207 uint32_t intstatus:32; 208 } field; 209 uint32_t word; 210 } gpio_intstatus_t; 211 212 /*! @name GPIOEN */ 213 typedef union 214 { 215 struct 216 { 217 /* GPIO clock enable configuration bitfield: 218 - bit[i]=1'b0: disable clock for GPIO[i] 219 - bit[i]=1'b1: enable clock for GPIO[i] 220 GPIOs are gathered by groups of 4. The clock gating of one group is done only if all 4 GPIOs are disabled. 221 Clock must be enabled for a GPIO if it's direction is configured in input mode. */ 222 uint32_t gpioen:32; 223 } field; 224 uint32_t word; 225 } gpio_gpioen_t; 226 227 /*! @name PADCFG */ 228 typedef union 229 { 230 struct 231 { 232 /* GPIO[0] pull activation configuration bitfield: 233 - 1'b0: pull disabled 234 - 1'b1: pull enabled */ 235 uint32_t gpio0_pe:1; 236 /* GPIO[0] drive strength configuration bitfield: 237 - 1'b0: low drive strength 238 - 1'b1: high drive strength */ 239 uint32_t gpio0_ds:1; 240 uint32_t reserved_0:6; 241 /* GPIO[1] pull activation configuration bitfield: 242 - 1'b0: pull disabled 243 - 1'b1: pull enabled */ 244 uint32_t gpio1_pe:1; 245 /* GPIO[1] drive strength configuration bitfield: 246 - 1'b0: low drive strength 247 - 1'b1: high drive strength */ 248 uint32_t gpio1_ds:1; 249 uint32_t reserved_1:6; 250 /* GPIO[2] pull activation configuration bitfield: 251 - 1'b0: pull disabled 252 - 1'b1: pull enabled */ 253 uint32_t gpio2_pe:1; 254 /* GPIO[2] drive strength configuration bitfield: 255 - 1'b0: low drive strength 256 - 1'b1: high drive strength */ 257 uint32_t gpio2_ds:1; 258 uint32_t reserved_2:6; 259 /* GPIO[3] pull activation configuration bitfield: 260 - 1'b0: pull disabled 261 - 1'b1: pull enabled */ 262 uint32_t gpio3_pe:1; 263 /* GPIO[3] drive strength configuration bitfield: 264 - 1'b0: low drive strength 265 - 1'b1: high drive strength */ 266 uint32_t gpio3_ds:1; 267 } field; 268 uint32_t word; 269 } gpio_padcfg_t; 270 271 272 /* ---------------------------------------------------------------------------- 273 274 CMD IDs and macros 275 276 ----------------------------------------------------------------------------*/ 277 278 #endif /* HAL_INCLUDE_HAL_GPIO_PERIPH_H_ */ 279