1 /*
2 * Copyright (c) 2021 HPMicro
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 *
6 */
7
8 #ifndef HPM_GPTMR_DRV_H
9 #define HPM_GPTMR_DRV_H
10 #include "hpm_common.h"
11 #include "hpm_gptmr_regs.h"
12 #include "hpm_soc_feature.h"
13
14 /**
15 * @brief GPTMR driver APIs
16 * @defgroup gptmr_interface GPTMR driver APIs
17 * @ingroup io_interfaces
18 * @{
19 */
20
21 /**
22 * @brief GPTMR channel IRQ mask
23 */
24 #define GPTMR_CH_CMP_IRQ_MASK(ch, cmp) (1 << (ch * 4 + 2 + cmp))
25 #define GPTMR_CH_CAP_IRQ_MASK(ch) (1 << (ch * 4 + 1))
26 #define GPTMR_CH_RLD_IRQ_MASK(ch) (1 << (ch * 4))
27
28 /**
29 * @brief GPTMR channel status
30 */
31 #define GPTMR_CH_CMP_STAT_MASK(ch, cmp) (1 << (ch * 4 + 2 + cmp))
32 #define GPTMR_CH_CAP_STAT_MASK(ch) (1 << (ch * 4 + 1))
33 #define GPTMR_CH_RLD_STAT_MASK(ch) (1 << (ch * 4))
34
35 /**
36 * @brief GPTMR channel swsynct mask
37 */
38 #define GPTMR_CH_GCR_SWSYNCT_MASK(ch) (1 << ch)
39
40 /**
41 * @brief GPTMR one channel support output comparator count
42 */
43 #define GPTMR_CH_CMP_COUNT (2U)
44
45 /**
46 * @brief GPTMR synci valid edge
47 */
48 typedef enum gptmr_synci_edge {
49 gptmr_synci_edge_none = 0,
50 gptmr_synci_edge_falling = GPTMR_CHANNEL_CR_SYNCIFEN_MASK,
51 gptmr_synci_edge_rising = GPTMR_CHANNEL_CR_SYNCIREN_MASK,
52 gptmr_synci_edge_both = gptmr_synci_edge_falling | gptmr_synci_edge_rising,
53 } gptmr_synci_edge_t;
54
55 /**
56 * @brief GPTMR work mode
57 */
58 typedef enum gptmr_work_mode {
59 gptmr_work_mode_no_capture = 0,
60 gptmr_work_mode_capture_at_rising_edge = 1,
61 gptmr_work_mode_capture_at_falling_edge = 2,
62 gptmr_work_mode_capture_at_both_edge = 3,
63 gptmr_work_mode_measure_width = 4,
64 } gptmr_work_mode_t;
65
66 /**
67 * @brief GPTMR DMA request event
68 */
69 typedef enum gptmr_dma_request_event {
70 gptmr_dma_request_on_cmp0 = 0,
71 gptmr_dma_request_on_cmp1 = 1,
72 gptmr_dma_request_on_input_signal_toggle = 2,
73 gptmr_dma_request_on_reload = 3,
74 gptmr_dma_request_disabled = 0xFF,
75 } gptmr_dma_request_event_t;
76
77 /**
78 * @brief GPTMR counter type
79 */
80 typedef enum gptmr_counter_type {
81 gptmr_counter_type_rising_edge,
82 gptmr_counter_type_falling_edge,
83 gptmr_counter_type_measured_period,
84 gptmr_counter_type_measured_duty_cycle,
85 gptmr_counter_type_normal,
86 } gptmr_counter_type_t;
87
88 /**
89 * @brief GPTMR counter mode
90 */
91
92 #if defined(HPM_IP_FEATURE_GPTMR_CNT_MODE) && (HPM_IP_FEATURE_GPTMR_CNT_MODE == 1)
93 typedef enum gptmr_counter_mode {
94 gptmr_counter_mode_internal = 0,
95 gptmr_counter_mode_external,
96 } gptmr_counter_mode_t;
97 #endif
98
99 /**
100 * @brief GPTMR channel config
101 */
102 typedef struct gptmr_channel_config {
103 gptmr_work_mode_t mode;
104 gptmr_dma_request_event_t dma_request_event;
105 gptmr_synci_edge_t synci_edge;
106 uint32_t cmp[GPTMR_CH_CMP_COUNT];
107 uint32_t reload;
108 bool cmp_initial_polarity_high;
109 bool enable_cmp_output;
110 bool enable_sync_follow_previous_channel;
111 bool enable_software_sync;
112 bool debug_mode;
113 } gptmr_channel_config_t;
114
115 #if defined(HPM_IP_FEATURE_GPTMR_MONITOR) && (HPM_IP_FEATURE_GPTMR_MONITOR == 1)
116 typedef enum gptmr_channel_monitor_type {
117 monitor_signal_period = 0,
118 monitor_signal_high_level_time,
119 } gptmr_channel_monitor_type_t;
120
121 typedef struct gptmr_channel_monitor_config {
122 gptmr_channel_monitor_type_t monitor_type;
123 uint32_t max_value; /**< The unit is the gptmr clock source period */
124 uint32_t min_value; /**< The unit is the gptmr clock source period */
125 } gptmr_channel_monitor_config_t;
126 #endif
127
128 #ifdef __cplusplus
129 extern "C" {
130 #endif
131
132 /**
133 * @brief gptmr channel enable
134 *
135 * @param [in] ptr GPTMR base address
136 * @param [in] ch_index channel index
137 * @param [in] enable
138 * @arg true: enable
139 * @arg false: disable
140 */
gptmr_channel_enable(GPTMR_Type * ptr,uint8_t ch_index,bool enable)141 static inline void gptmr_channel_enable(GPTMR_Type *ptr, uint8_t ch_index, bool enable)
142 {
143 ptr->CHANNEL[ch_index].CR = (ptr->CHANNEL[ch_index].CR
144 & ~(GPTMR_CHANNEL_CR_CNTRST_MASK | GPTMR_CHANNEL_CR_CMPEN_MASK))
145 | GPTMR_CHANNEL_CR_CMPEN_SET(enable);
146 }
147
148 /**
149 * @brief gptmr channel reset counter
150 *
151 * @param [in] ptr GPTMR base address
152 * @param [in] ch_index channel index
153 */
gptmr_channel_reset_count(GPTMR_Type * ptr,uint8_t ch_index)154 static inline void gptmr_channel_reset_count(GPTMR_Type *ptr, uint8_t ch_index)
155 {
156 ptr->CHANNEL[ch_index].CR |= GPTMR_CHANNEL_CR_CNTRST_MASK;
157 ptr->CHANNEL[ch_index].CR &= ~GPTMR_CHANNEL_CR_CNTRST_MASK;
158 }
159
160 /**
161 * @brief gptmr channel update counter
162 *
163 * @param [in] ptr GPTMR base address
164 * @param [in] ch_index channel index
165 * @param [in] value updated vaue
166 */
gptmr_channel_update_count(GPTMR_Type * ptr,uint8_t ch_index,uint32_t value)167 static inline void gptmr_channel_update_count(GPTMR_Type *ptr,
168 uint8_t ch_index,
169 uint32_t value)
170 {
171 if (value > 0) {
172 value--;
173 }
174 ptr->CHANNEL[ch_index].CNTUPTVAL = GPTMR_CHANNEL_CNTUPTVAL_CNTUPTVAL_SET(value);
175 ptr->CHANNEL[ch_index].CR |= GPTMR_CHANNEL_CR_CNTUPT_MASK;
176 }
177
178 /**
179 * @brief gptmr channel slect synci valid edge
180 *
181 * @param [in] ptr GPTMR base address
182 * @param [in] ch_index channel index
183 * @param [in] edge gptmr_synci_edge_t
184 */
gptmr_channel_select_synci_valid_edge(GPTMR_Type * ptr,uint8_t ch_index,gptmr_synci_edge_t edge)185 static inline void gptmr_channel_select_synci_valid_edge(GPTMR_Type *ptr,
186 uint8_t ch_index,
187 gptmr_synci_edge_t edge)
188 {
189 ptr->CHANNEL[ch_index].CR = (ptr->CHANNEL[ch_index].CR
190 & ~(GPTMR_CHANNEL_CR_SYNCIFEN_MASK
191 | GPTMR_CHANNEL_CR_SYNCIREN_MASK)) | edge;
192 }
193
194 /**
195 * @brief gptmr channel enable dma request
196 *
197 * @param [in] ptr GPTMR base address
198 * @param [in] ch_index channel index
199 * @param [in] enable
200 * @arg true: enable
201 * @arg false: disable
202 */
gptmr_channel_enable_dma_request(GPTMR_Type * ptr,uint8_t ch_index,bool enable)203 static inline void gptmr_channel_enable_dma_request(GPTMR_Type *ptr,
204 uint8_t ch_index,
205 bool enable)
206 {
207 ptr->CHANNEL[ch_index].CR = (ptr->CHANNEL[ch_index].CR
208 & ~(GPTMR_CHANNEL_CR_DMAEN_MASK)) | GPTMR_CHANNEL_CR_DMAEN_SET(enable);
209 }
210
211 /**
212 * @brief gptmr channel get counter value
213 *
214 * @param [in] ptr GPTMR base address
215 * @param [in] ch_index channel index
216 * @param [in] capture gptmr_counter_type_t
217 */
gptmr_channel_get_counter(GPTMR_Type * ptr,uint8_t ch_index,gptmr_counter_type_t capture)218 static inline uint32_t gptmr_channel_get_counter(GPTMR_Type *ptr,
219 uint8_t ch_index,
220 gptmr_counter_type_t capture)
221 {
222 uint32_t value;
223 switch (capture) {
224 case gptmr_counter_type_rising_edge:
225 value = (ptr->CHANNEL[ch_index].CAPPOS & GPTMR_CHANNEL_CAPPOS_CAPPOS_MASK) >> GPTMR_CHANNEL_CAPPOS_CAPPOS_SHIFT;
226 break;
227 case gptmr_counter_type_falling_edge:
228 value = (ptr->CHANNEL[ch_index].CAPNEG & GPTMR_CHANNEL_CAPNEG_CAPNEG_MASK) >> GPTMR_CHANNEL_CAPNEG_CAPNEG_SHIFT;
229 break;
230 case gptmr_counter_type_measured_period:
231 value = (ptr->CHANNEL[ch_index].CAPPRD & GPTMR_CHANNEL_CAPPRD_CAPPRD_MASK) >> GPTMR_CHANNEL_CAPPRD_CAPPRD_SHIFT;
232 break;
233 case gptmr_counter_type_measured_duty_cycle:
234 value = (ptr->CHANNEL[ch_index].CAPDTY & GPTMR_CHANNEL_CAPDTY_MEAS_HIGH_MASK) >> GPTMR_CHANNEL_CAPDTY_MEAS_HIGH_SHIFT;
235 break;
236 default:
237 value = (ptr->CHANNEL[ch_index].CNT & GPTMR_CHANNEL_CNT_COUNTER_MASK) >> GPTMR_CHANNEL_CNT_COUNTER_SHIFT;
238 break;
239 }
240 return value;
241 }
242
243 /**
244 * @brief gptmr trigger channel software sync
245 *
246 * @param [in] ptr GPTMR base address
247 * @param [in] ch_index_mask channel index mask
248 */
gptmr_trigger_channel_software_sync(GPTMR_Type * ptr,uint32_t ch_index_mask)249 static inline void gptmr_trigger_channel_software_sync(GPTMR_Type *ptr, uint32_t ch_index_mask)
250 {
251 ptr->GCR = ch_index_mask;
252 }
253
254 /**
255 * @brief gptmr enable irq
256 *
257 * @param [in] ptr GPTMR base address
258 * @param [in] irq_mask irq mask
259 */
gptmr_enable_irq(GPTMR_Type * ptr,uint32_t irq_mask)260 static inline void gptmr_enable_irq(GPTMR_Type *ptr, uint32_t irq_mask)
261 {
262 ptr->IRQEN |= irq_mask;
263 }
264
265 /**
266 * @brief gptmr disable irq
267 *
268 * @param [in] ptr GPTMR base address
269 * @param [in] irq_mask irq mask
270 */
gptmr_disable_irq(GPTMR_Type * ptr,uint32_t irq_mask)271 static inline void gptmr_disable_irq(GPTMR_Type *ptr, uint32_t irq_mask)
272 {
273 ptr->IRQEN &= ~irq_mask;
274 }
275
276 /**
277 * @brief gptmr check status
278 *
279 * @param [in] ptr GPTMR base address
280 * @param [in] mask channel flag mask
281 */
gptmr_check_status(GPTMR_Type * ptr,uint32_t mask)282 static inline bool gptmr_check_status(GPTMR_Type *ptr, uint32_t mask)
283 {
284 return (ptr->SR & mask) == mask;
285 }
286
287 /**
288 * @brief gptmr clear status
289 *
290 * @param [in] ptr GPTMR base address
291 * @param [in] mask channel flag mask
292 */
gptmr_clear_status(GPTMR_Type * ptr,uint32_t mask)293 static inline void gptmr_clear_status(GPTMR_Type *ptr, uint32_t mask)
294 {
295 ptr->SR = mask;
296 }
297
298 /**
299 * @brief gptmr get status
300 *
301 * @param [in] ptr GPTMR base address
302 * @retval SR register value
303 */
gptmr_get_status(GPTMR_Type * ptr)304 static inline uint32_t gptmr_get_status(GPTMR_Type *ptr)
305 {
306 return ptr->SR;
307 }
308
309 /**
310 * @brief gptmr channel start counter
311 *
312 * @param [in] ptr GPTMR base address
313 * @param [in] ch_index channel index
314 */
gptmr_start_counter(GPTMR_Type * ptr,uint8_t ch_index)315 static inline void gptmr_start_counter(GPTMR_Type *ptr, uint8_t ch_index)
316 {
317 ptr->CHANNEL[ch_index].CR |= GPTMR_CHANNEL_CR_CEN_MASK;
318 }
319
320 /**
321 * @brief gptmr channel stop counter
322 *
323 * @param [in] ptr GPTMR base address
324 * @param [in] ch_index channel index
325 */
gptmr_stop_counter(GPTMR_Type * ptr,uint8_t ch_index)326 static inline void gptmr_stop_counter(GPTMR_Type *ptr, uint8_t ch_index)
327 {
328 ptr->CHANNEL[ch_index].CR &= ~GPTMR_CHANNEL_CR_CEN_MASK;
329 }
330
331 /**
332 * @brief gptmr channel enable compare output
333 *
334 * @param [in] ptr GPTMR base address
335 * @param [in] ch_index channel index
336 */
gptmr_enable_cmp_output(GPTMR_Type * ptr,uint8_t ch_index)337 static inline void gptmr_enable_cmp_output(GPTMR_Type *ptr, uint8_t ch_index)
338 {
339 ptr->CHANNEL[ch_index].CR |= GPTMR_CHANNEL_CR_CMPEN_MASK;
340 }
341
342 /**
343 * @brief gptmr channel disable compare output
344 *
345 * @param [in] ptr GPTMR base address
346 * @param [in] ch_index channel index
347 */
gptmr_disable_cmp_output(GPTMR_Type * ptr,uint8_t ch_index)348 static inline void gptmr_disable_cmp_output(GPTMR_Type *ptr, uint8_t ch_index)
349 {
350 ptr->CHANNEL[ch_index].CR &= ~GPTMR_CHANNEL_CR_CMPEN_MASK;
351 }
352
353 /**
354 * @brief gptmr channel set capmode
355 *
356 * @param [in] ptr GPTMR base address
357 * @param [in] ch_index channel index
358 * @param [in] mode enum gptmr_work_mode_capture_at_rising_edge or gptmr_work_mode_capture_at_falling_edge and so on
359 */
gptmr_channel_set_capmode(GPTMR_Type * ptr,uint8_t ch_index,gptmr_work_mode_t mode)360 static inline void gptmr_channel_set_capmode(GPTMR_Type *ptr, uint8_t ch_index, gptmr_work_mode_t mode)
361 {
362 ptr->CHANNEL[ch_index].CR = (ptr->CHANNEL[ch_index].CR & ~GPTMR_CHANNEL_CR_CAPMODE_MASK) | GPTMR_CHANNEL_CR_CAPMODE_SET(mode);
363 }
364
365 /**
366 * @brief gptmr channel get capmode
367 *
368 * @param [in] ptr GPTMR base address
369 * @param [in] ch_index channel index
370 * @retval gptmr_work_mode_t enum gptmr_work_mode_capture_at_rising_edge or gptmr_work_mode_capture_at_falling_edge
371 */
gptmr_channel_get_capmode(GPTMR_Type * ptr,uint8_t ch_index)372 static inline gptmr_work_mode_t gptmr_channel_get_capmode(GPTMR_Type *ptr, uint8_t ch_index)
373 {
374 return (gptmr_work_mode_t)GPTMR_CHANNEL_CR_CAPMODE_GET(ptr->CHANNEL[ch_index].CR);
375 }
376
377 /**
378 * @brief gptmr channel update comparator
379 *
380 * @param [in] ptr GPTMR base address
381 * @param [in] ch_index channel index
382 * @param [in] cmp_index comparator index
383 * @param [in] cmp comparator value
384 */
gptmr_update_cmp(GPTMR_Type * ptr,uint8_t ch_index,uint8_t cmp_index,uint32_t cmp)385 static inline void gptmr_update_cmp(GPTMR_Type *ptr, uint8_t ch_index, uint8_t cmp_index, uint32_t cmp)
386 {
387 if (cmp > 0) {
388 cmp--;
389 }
390 ptr->CHANNEL[ch_index].CMP[cmp_index] = GPTMR_CHANNEL_CMP_CMP_SET(cmp);
391 }
392
393 /**
394 * @brief gptmr channel get reload
395 *
396 * @param [in] ptr GPTMR base address
397 * @param [in] ch_index channel index
398 * @retval RLD register value
399 */
gptmr_channel_get_reload(GPTMR_Type * ptr,uint8_t ch_index)400 static inline uint32_t gptmr_channel_get_reload(GPTMR_Type *ptr, uint8_t ch_index)
401 {
402 return ptr->CHANNEL[ch_index].RLD;
403 }
404
405 /**
406 * @brief gptmr channel update reload
407 *
408 * @param [in] ptr GPTMR base address
409 * @param [in] ch_index channel index
410 * @param [in] reload reload value
411 */
gptmr_channel_config_update_reload(GPTMR_Type * ptr,uint8_t ch_index,uint32_t reload)412 static inline void gptmr_channel_config_update_reload(GPTMR_Type *ptr, uint8_t ch_index, uint32_t reload)
413 {
414 if (reload > 0) {
415 reload--;
416 }
417 ptr->CHANNEL[ch_index].RLD = GPTMR_CHANNEL_RLD_RLD_SET(reload);
418 }
419
420 /**
421 * @brief gptmr channel get dma request event
422 *
423 * @param [in] ptr GPTMR base address
424 * @param [in] ch_index channel index
425 * @retval gptmr_dma_request_event_t gptmr_dma_request_on_cmp0 or gptmr_dma_request_on_reload
426 */
gptmr_channel_get_dma_request_event(GPTMR_Type * ptr,uint8_t ch_index)427 static inline gptmr_dma_request_event_t gptmr_channel_get_dma_request_event(GPTMR_Type *ptr, uint8_t ch_index)
428 {
429 return (gptmr_dma_request_event_t)GPTMR_CHANNEL_CR_DMASEL_GET(ptr->CHANNEL[ch_index].CR);
430 }
431
432 /**
433 * @brief gptmr channel config
434 *
435 * @param [in] ptr GPTMR base address
436 * @param [in] ch_index channel index
437 * @param [in] config gptmr_channel_config_t
438 * @param [in] enable
439 * @arg true: enable
440 * @arg false: disable
441 *
442 * @retval hpm_stat_t status_invalid_argument or status_success
443 */
444 hpm_stat_t gptmr_channel_config(GPTMR_Type *ptr,
445 uint8_t ch_index,
446 gptmr_channel_config_t *config,
447 bool enable);
448
449 /**
450 * @brief gptmr channel get default config
451 *
452 * @param [in] ptr GPTMR base address
453 * @param [out] config gptmr_channel_config_t
454 */
455 void gptmr_channel_get_default_config(GPTMR_Type *ptr, gptmr_channel_config_t *config);
456
457
458 #if defined(HPM_IP_FEATURE_GPTMR_CNT_MODE) && (HPM_IP_FEATURE_GPTMR_CNT_MODE == 1)
459 /**
460 * @brief gptmr set counter mode.
461 *
462 * @param [in] ptr GPTMR base address
463 * @param [in] ch_index channel index
464 * @param [in] mode gptmr_counter_mode_t, gptmr_counter_mode_external for gptmr enable external counting mode
465 */
gptmr_channel_set_counter_mode(GPTMR_Type * ptr,uint8_t ch_index,gptmr_counter_mode_t mode)466 static inline void gptmr_channel_set_counter_mode(GPTMR_Type *ptr, uint8_t ch_index, gptmr_counter_mode_t mode)
467 {
468 ptr->CHANNEL[ch_index].CR = (ptr->CHANNEL[ch_index].CR & ~GPTMR_CHANNEL_CR_CNT_MODE_MASK) | GPTMR_CHANNEL_CR_CNT_MODE_SET(mode);
469 }
470
471 /**
472 * @brief gptmr channel get external trigger input counting mode.
473 *
474 * @param [in] ptr GPTMR base address
475 * @param [in] ch_index channel index
476 * @retval gptmr_counter_mode_external for external counting mode, gptmr_counter_mode_internal for internal counting mode
477 */
gptmr_channel_get_counter_mode(GPTMR_Type * ptr,uint8_t ch_index)478 static inline gptmr_counter_mode_t gptmr_channel_get_counter_mode(GPTMR_Type *ptr, uint8_t ch_index)
479 {
480 return ((ptr->CHANNEL[ch_index].CR & GPTMR_CHANNEL_CR_CNT_MODE_MASK) ==
481 GPTMR_CHANNEL_CR_CNT_MODE_MASK) ?
482 gptmr_counter_mode_external : gptmr_counter_mode_internal;
483 }
484
485 #endif
486
487 #if defined(HPM_IP_FEATURE_GPTMR_OP_MODE) && (HPM_IP_FEATURE_GPTMR_OP_MODE == 1)
488 /**
489 * @brief gptmr channel enable opmode, it's one-shot mode, timer will stopped at reload point.
490 *
491 * @note reload irq will be always set at one-shot mode at end
492 *
493 * @param [in] ptr GPTMR base address
494 * @param [in] ch_index channel index
495 */
gptmr_channel_enable_opmode(GPTMR_Type * ptr,uint8_t ch_index)496 static inline void gptmr_channel_enable_opmode(GPTMR_Type *ptr, uint8_t ch_index)
497 {
498 ptr->CHANNEL[ch_index].CR |= GPTMR_CHANNEL_CR_OPMODE_MASK;
499 }
500
501 /**
502 * @brief gptmr channel disable opmode, it's round mode.
503 *
504 * @param [in] ptr GPTMR base address
505 * @param [in] ch_index channel index
506 */
gptmr_channel_disable_opmode(GPTMR_Type * ptr,uint8_t ch_index)507 static inline void gptmr_channel_disable_opmode(GPTMR_Type *ptr, uint8_t ch_index)
508 {
509 ptr->CHANNEL[ch_index].CR &= ~GPTMR_CHANNEL_CR_OPMODE_MASK;
510 }
511
512 /**
513 * @brief gptmr channel get opmode.
514 *
515 * @param [in] ptr GPTMR base address
516 * @param [in] ch_index channel index
517 * @retval bool true for opmode, false for normal mode
518 */
gptmr_channel_is_opmode(GPTMR_Type * ptr,uint8_t ch_index)519 static inline bool gptmr_channel_is_opmode(GPTMR_Type *ptr, uint8_t ch_index)
520 {
521 return ((ptr->CHANNEL[ch_index].CR & GPTMR_CHANNEL_CR_OPMODE_MASK) == GPTMR_CHANNEL_CR_OPMODE_MASK) ? true : false;
522 }
523 #endif
524
525 #if defined(HPM_IP_FEATURE_GPTMR_MONITOR) && (HPM_IP_FEATURE_GPTMR_MONITOR == 1)
526 /**
527 * @brief gptmr channel enable monitor, set to monitor input signal period or high level time.
528 *
529 * @param [in] ptr GPTMR base address
530 * @param [in] ch_index channel index
531 */
gptmr_channel_enable_monitor(GPTMR_Type * ptr,uint8_t ch_index)532 static inline void gptmr_channel_enable_monitor(GPTMR_Type *ptr, uint8_t ch_index)
533 {
534 ptr->CHANNEL[ch_index].CR |= GPTMR_CHANNEL_CR_MONITOR_EN_MASK;
535 }
536
537 /**
538 * @brief gptmr channel disable monitor
539 *
540 * @param [in] ptr GPTMR base address
541 * @param [in] ch_index channel index
542 */
gptmr_channel_disable_monitor(GPTMR_Type * ptr,uint8_t ch_index)543 static inline void gptmr_channel_disable_monitor(GPTMR_Type *ptr, uint8_t ch_index)
544 {
545 ptr->CHANNEL[ch_index].CR &= ~GPTMR_CHANNEL_CR_MONITOR_EN_MASK;
546 }
547
548 /**
549 * @brief gptmr channel set to monitor input signal period or high level time.
550 *
551 * @param [in] ptr GPTMR base address
552 * @param [in] ch_index channel index
553 * @param [in] type gptmr_channel_monitor_type_t
554 */
gptmr_channel_set_monitor_type(GPTMR_Type * ptr,uint8_t ch_index,gptmr_channel_monitor_type_t type)555 static inline void gptmr_channel_set_monitor_type(GPTMR_Type *ptr, uint8_t ch_index, gptmr_channel_monitor_type_t type)
556 {
557 ptr->CHANNEL[ch_index].CR = (ptr->CHANNEL[ch_index].CR & ~GPTMR_CHANNEL_CR_MONITOR_SEL_MASK) | GPTMR_CHANNEL_CR_MONITOR_SEL_SET(type);
558 }
559
560 /**
561 * @brief gptmr channel get to monitor input signal period or high level time.
562 *
563 * @param [in] ptr GPTMR base address
564 * @param [in] ch_index channel index
565 * @retval gptmr_channel_monitor_type_t monitor_signal_high_level_time or monitor_signal_period
566 */
gptmr_channel_get_monitor_type(GPTMR_Type * ptr,uint8_t ch_index)567 static inline gptmr_channel_monitor_type_t gptmr_channel_get_monitor_type(GPTMR_Type *ptr, uint8_t ch_index)
568 {
569 return (gptmr_channel_monitor_type_t)GPTMR_CHANNEL_CR_MONITOR_SEL_GET(ptr->CHANNEL[ch_index].CR);
570 }
571 /**
572 * @brief gptmr channel get default monitor config
573 *
574 * @param [in] ptr GPTMR base address
575 * @param [out] config gptmr_channel_monitor_config_t
576 */
577 void gptmr_channel_get_default_monitor_config(GPTMR_Type *ptr, gptmr_channel_monitor_config_t *config);
578
579 /**
580 * @brief gptmr channel monitor config
581 *
582 * @param [in] ptr GPTMR base address
583 * @param [in] ch_index channel index
584 * @param [in] config gptmr_channel_monitor_config_t
585 * @param [in] enable
586 * @arg true: enable monitor and reset reload count
587 * @arg false: disable monitor
588 *
589 * @retval hpm_stat_t status_invalid_argument or status_success
590 */
591
592 hpm_stat_t gptmr_channel_monitor_config(GPTMR_Type *ptr, uint8_t ch_index,
593 gptmr_channel_monitor_config_t *config,
594 bool enable);
595
596 #endif
597
598
599 /**
600 * @}
601 */
602
603 #ifdef __cplusplus
604 }
605 #endif
606
607 #endif /* HPM_GPTMR_DRV_H */
608