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Searched refs:hal_readl (Results 1 – 22 of 22) sorted by relevance

/bsp/allwinner/libraries/sunxi-hal/hal/source/gmac/
A Dhal_geth_utils.c43 sid3 = hal_readl(0x03006200 + 0xc); in random_ether_addr()
102 value = hal_readl(iobase + GETH_TX_CTL1); in geth_start_tx()
111 value = hal_readl(iobase + GETH_TX_CTL1); in geth_stop_tx()
120 value = hal_readl(iobase + GETH_RX_CTL1); in geth_start_rx()
129 value = hal_readl(iobase + GETH_RX_CTL1); in geth_stop_rx()
173 value = hal_readl(iobase + GETH_TX_CTL1); in geth_mac_init()
178 value = hal_readl(iobase + GETH_RX_CTL0); in geth_mac_init()
181 value = hal_readl(iobase + GETH_RX_CTL1); in geth_mac_init()
279 value = hal_readl(iobase + GETH_INT_EN); in geth_rx_int_disable()
286 value = hal_readl(iobase + GETH_INT_EN); in geth_tx_int_disable()
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A Dhal_geth.c233 int_sta_value = hal_readl(rt_geth_dev.iobase + GETH_INT_STA); in geth_irq_handler()
681 value = hal_readl(rt_geth_dev.iobase + GETH_BASIC_CTL1); in rt_geth_init()
/bsp/allwinner/libraries/sunxi-hal/hal/source/ledc/
A Dhal_ledc.c93 reg_val = hal_readl(base_addr + LED_RST_TIMING_CTRL_REG); in ledc_set_reset_ns()
113 reg_val = hal_readl(base_addr + LED_T01_TIMING_CTRL_REG); in ledc_set_t1h_ns()
241 reg_val = hal_readl(base_addr + LEDC_CTRL_REG); in ledc_set_length()
276 reg_val = hal_readl(base_addr + LEDC_CTRL_REG); in ledc_set_output_mode()
286 reg_val = hal_readl(base_addr + LEDC_INTC_REG); in ledc_disable_irq()
295 reg_val = hal_readl(base_addr + LEDC_INTC_REG); in ledc_enable_irq()
320 reg_val = hal_readl(base_addr + LEDC_INTS_REG); in ledc_clear_all_irq()
327 return hal_readl(base_addr + LEDC_INTS_REG); in ledc_get_irq_status()
334 reg_val = hal_readl(base_addr + LEDC_CTRL_REG); in ledc_soft_reset()
343 reg_val = hal_readl(base_addr + LEDC_CTRL_REG); in ledc_reset_en()
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/bsp/allwinner/libraries/sunxi-hal/hal/source/pwm/
A Dhal_pwm.c98 reg_val = hal_readl(reg_addr); in hal_pwm_clk_src_set()
116 reg_val = hal_readl(reg_addr); in hal_pwm_clk_div_m()
130 reg_val = hal_readl(reg_addr); in hal_pwm_prescal_set()
146 reg_val = hal_readl(reg_addr); in hal_pwm_set_active_cycles()
160 reg_val = hal_readl(reg_addr); in hal_pwm_set_period_cycles()
204 reg_val = hal_readl(reg_addr); in hal_pwm_enable_clk_gating()
242 reg_val = hal_readl(reg_addr); in hal_pwm_porality()
489 temp = hal_readl(PWM_BASE + reg_offset); in hal_pwm_control()
495 value = hal_readl(PWM_BASE + PWM_PCGR); in hal_pwm_control()
503 temp = hal_readl(PWM_BASE + reg_offset); in hal_pwm_control()
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/bsp/allwinner/libraries/sunxi-hal/hal/source/ir/
A Dhal_ir.c56 return (u8)(hal_readl(reg_base + IR_RXDAT_REG) & 0xff); in ir_get_data()
61 return hal_readl(reg_base + IR_RXINTS_REG); in ir_get_intsta()
66 uint32_t tmp = hal_readl(reg_base + IR_RXINTS_REG); in ir_clr_intsta()
120 ctrl_reg = hal_readl(reg_base + IR_CTRL_REG); in ir_mode_set()
124 ctrl_reg = hal_readl(reg_base + IR_CTRL_REG); in ir_mode_set()
128 ctrl_reg = hal_readl(reg_base + IR_CTRL_REG); in ir_mode_set()
132 ctrl_reg = hal_readl(reg_base + IR_CTRL_REG); in ir_mode_set()
136 ctrl_reg = hal_readl(reg_base + IR_CTRL_REG); in ir_mode_set()
151 sample_reg = hal_readl(reg_base + IR_SPLCFG_REG); in ir_sample_config()
202 irq_reg = hal_readl(reg_base + IR_RXINTE_REG); in ir_irq_config()
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/bsp/allwinner/libraries/sunxi-hal/hal/source/lradc/
A Dhal_lradc.c49 reg_val = hal_readl(base_addr + LRADC_CTRL_REG); in lradc_ctrl_set()
58 reg_val = hal_readl(base_addr + LRADC_CTRL_REG); in lradc_ctrl_reset()
67 reg_val = hal_readl(base_addr + LRADC_INTC_REG); in lradc_irq_set()
76 reg_val = hal_readl(base_addr + LRADC_INTC_REG); in lradc_irq_reset()
92 uint32_t irq_status = hal_readl(base_addr + LRADC_INTS_REG); in lradc_irq_handler()
93 uint32_t reg_val = hal_readl(base_addr + LRADC_DATA0_REG); in lradc_irq_handler()
/bsp/allwinner/libraries/sunxi-hal/hal/source/timer/
A Dsunxi_timer.c59 uint32_t old = hal_readl((unsigned long)TIMER_CNTVAL_REG(timer)); in sunxi_timer_sync()
61 while ((old - hal_readl((unsigned long)TIMER_CNTVAL_REG(timer))) < TIMER_SYNC_TICKS) in sunxi_timer_sync()
71 return hal_readl((unsigned long)TIMER_CNTVAL_REG(timer)); in sunxi_timer_get_count()
76 uint32_t val = hal_readl((unsigned long)TIMER_CTL_REG(timer)); in sunxi_timer_stop()
85 uint32_t val = hal_readl((unsigned long)TIMER_CTL_REG(timer)); in sunxi_timer_start()
161 val = hal_readl((unsigned long)TIMER_CTL_REG(id)); in sunxi_timer_init()
181 val = hal_readl((unsigned long)TIMER_IRQ_EN_REG); in sunxi_timer_init()
A Dhal_avs.c21 val = hal_readl(avs->base + AVS_CNT_CTRL_REG); in hal_avs_continue()
39 val = hal_readl(avs->base + AVS_CNT_CTRL_REG); in hal_avs_pause()
57 val = hal_readl(avs->base + AVS_CNT_CTRL_REG); in hal_avs_disable()
75 val = hal_readl(avs->base + AVS_CNT_CTRL_REG); in hal_avs_enable()
92 *counter = hal_readl(avs->base + AVS_CNT_REG(id)); in hal_avs_get_counter()
126 val = hal_readl(avs->base + AVS_CNT_DIV_REG); in hal_avs_set_cnt_div()
/bsp/allwinner/libraries/sunxi-hal/hal/source/rtc/
A Dhal_rtc.c166 val = hal_readl(rtc_dev->base + SUNXI_ALRM_IRQ_STA); in hal_rtc_alarmirq()
191 alrm_val = hal_readl(rtc_dev->base + SUNXI_ALRM_EN); in hal_rtc_setaie()
214 reg = hal_readl(rtc_dev->base + offset); in hal_rtc_wait()
303 date = hal_readl(rtc_dev->base + SUNXI_RTC_YMD); in hal_rtc_gettime()
304 time = hal_readl(rtc_dev->base + SUNXI_RTC_HMS); in hal_rtc_gettime()
480 alrm = hal_readl(rtc_dev->base + SUNXI_ALRM_DHMS); in hal_rtc_getalarm()
481 date = hal_readl(rtc_dev->base + SUNXI_RTC_YMD); in hal_rtc_getalarm()
532 alrm_en = hal_readl(rtc_dev->base + SUNXI_ALRM_IRQ_EN); in hal_rtc_getalarm()
714 tmp_data = hal_readl(rtc_dev->base + SUNXI_LOSC_CTRL); in hal_rtc_init()
721 tmp_data = hal_readl(rtc_dev->base + SUNXI_LOSC_CTRL); in hal_rtc_init()
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/bsp/allwinner/libraries/sunxi-hal/hal/source/dma/
A Dhal_dma.c153 (uint32_t)hal_readl(DMA_IRQ_EN(0)), in sunxi_dump_com_regs()
154 (uint32_t)hal_readl(DMA_IRQ_EN(1)), in sunxi_dump_com_regs()
155 (uint32_t)hal_readl(DMA_IRQ_STAT(0)), in sunxi_dump_com_regs()
156 (uint32_t)hal_readl(DMA_IRQ_STAT(1)), in sunxi_dump_com_regs()
158 (uint32_t)hal_readl(DMA_SECURE), in sunxi_dump_com_regs()
161 (uint32_t)hal_readl(DMA_GATE), in sunxi_dump_com_regs()
163 (uint32_t)hal_readl(DMA_STAT)); in sunxi_dump_com_regs()
223 status_l = hal_readl(DMA_IRQ_STAT(0)); in sunxi_dma_irq_handle()
225 status_h = hal_readl(DMA_IRQ_STAT(1)); in sunxi_dma_irq_handle()
720 irq_val = hal_readl(DMA_IRQ_EN(high)); in hal_dma_start()
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/bsp/allwinner/libraries/sunxi-hal/hal/source/spi/
A Dhal_spi.c134 uint32_t reg_val = hal_readl(sspi->base + SPI_TC_REG); in spi_set_cs()
156 uint32_t reg_val = hal_readl(sspi->base + SPI_TC_REG); in spi_config_dhb()
174 uint32_t reg_val = hal_readl(sspi->base + SPI_TC_REG); in spi_config_tc()
246 uint32_t reg_val = hal_readl(sspi->base + SPI_TC_REG); in spi_sample_delay()
276 uint32_t reg_val = hal_readl(sspi->base + SPI_TC_REG); in spi_start_xfer()
285 uint32_t reg_val = hal_readl(sspi->base + SPI_GC_REG); in spi_enable_bus()
294 uint32_t reg_val = hal_readl(sspi->base + SPI_GC_REG); in spi_disable_bus()
330 u32 reg_val = hal_readl(sspi->base + SPI_TC_REG); in spi_ss_owner()
462 reg_val = hal_readl(sspi->base + SPI_BURST_CNT_REG); in spi_set_bc_tc_stc()
474 reg_val = hal_readl(sspi->base + SPI_BCC_REG); in spi_set_bc_tc_stc()
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/bsp/allwinner/libraries/sunxi-hal/hal/source/efuse/
A Defuse.c123 reg_val = hal_readl((unsigned long)SID_PRCTL); in _efuse_reg_read_key()
130 while(hal_readl(SID_PRCTL)&0x2){}; in _efuse_reg_read_key()
133 reg_val = hal_readl((unsigned long)SID_RDKEY); in _efuse_reg_read_key()
154 reg_val = hal_readl((unsigned long)SID_PRCTL); in _efuse_program_key()
161 while(hal_readl((unsigned long)SID_PRCTL)&0x1){}; in _efuse_program_key()
232 return hal_readl((unsigned long)EFUSE_SRAM + key_index); in efuse_sram_read_key()
A Dhal_efuse.c208 return hal_readl(EFUSE_SECURE_MODE) & 0x1; in hal_efuse_get_security_mode()
/bsp/allwinner/libraries/sunxi-hal/hal/source/thermal/
A Dhal_thermal.c73 …hal_writel((hal_readl((unsigned long)THS_CALIB) & TEMP_CALIB_MASK) | (cdata << 16), (unsigned long… in hal_ths_calibrate()
125 val = hal_readl((unsigned long)THS_DATA + 0x4 * num); in hal_ths_get_temp()
/bsp/allwinner/libraries/sunxi-hal/hal/source/gpio/
A Dhal_gpio.c365 regval = hal_readl(gpio_desc->membase + reg); in gpio_irq_set_type()
400 val = hal_readl(gpio_desc->membase + reg); in gpio_irq_handle()
483 reg = hal_readl(gpio_desc->membase + offset); in gpio_conf_set()
509 val = (hal_readl(gpio_desc->membase + offset) >> shift) & mask; in gpio_conf_get()
716 temp = hal_readl(gpio_desc->membase + POWER_MODE_SEL); in hal_gpio_sel_vol_mode()
722 temp = hal_readl(gpio_desc->membase + POWER_VOL_SEL); in hal_gpio_sel_vol_mode()
758 reg_val = hal_readl(gpio_desc->membase + reg); in hal_gpio_set_debounce()
908 val = hal_readl(gpio_desc->membase + reg); in hal_gpio_irq_enable()
1004 val = hal_readl(gpio_desc->membase + reg); in hal_gpio_irq_disable()
/bsp/allwinner/libraries/sunxi-hal/hal/source/eise/
A Dhal_eise.c60 irq_status = hal_readl(pHe->eise_base_addr + EISE_INTERRUPT_STATUS); in eise_interrupt()
134 rData = hal_readl(pHe->eise_base_addr + reg.addr); in eise_hal_ctl()
/bsp/allwinner/libraries/drivers/
A Ddrv_uart.c690 while (!(hal_readl(uart_base + UART_USR) & UART_USR_TFNF)) in _uart_putc()
696 while (!(hal_readl(uart_base + UART_LSR) & UART_LSR_TEMT)) in _uart_putc()
711 while (!(hal_readl(uart_base + UART_RFL) & 0x1FFu)) in _uart_getc()
715 if (hal_readl(uart_base + UART_USR) & UART_USR_RFNE) in _uart_getc()
740 while (remain && (hal_readl(uart_base + UART_USR) & UART_USR_TFNF)) in _uart_transmit()
750 if (hal_readl(uart_base + UART_LSR) & UART_LSR_TEMT) in _uart_transmit()
769 if (hal_readl(uart_base + UART_LSR) & UART_LSR_TEMT) in _uart_transmit()
/bsp/allwinner/libraries/sunxi-hal/hal/source/usb/udc/
A Dudc_platform.h277 #define DRV_Reg32(addr) hal_readl(addr)
283 #define USB_DRV_Reg32(addr) hal_readl(addr)
/bsp/allwinner/libraries/sunxi-hal/hal/source/watchdog/
A Dhal_watchdog.c12 #define readl_wdt hal_readl
/bsp/allwinner/libraries/sunxi-hal/include/hal/
A Dsunxi_hal_common.h106 #define hal_readl(reg) (*(volatile uint32_t *)(reg)) macro
/bsp/allwinner/libraries/sunxi-hal/hal/source/usb/host/
A Dehci-sunxi.c204 HC_LENGTH(ehci, hal_readl(&ehci->caps->hc_capbase))); in sunxi_insmod_ehci()
207 ehci->hcs_params = hal_readl(&ehci->caps->hcs_params); in sunxi_insmod_ehci()
/bsp/allwinner/libraries/sunxi-hal/include/hal/sdmmc/
A Dsdio.h46 #define readl hal_readl

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