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Searched refs:hal_writel (Results 1 – 19 of 19) sorted by relevance

/bsp/allwinner/libraries/sunxi-hal/hal/source/gmac/
A Dhal_geth_utils.c104 hal_writel(value, iobase + GETH_TX_CTL1); in geth_start_tx()
113 hal_writel(value, iobase + GETH_TX_CTL1); in geth_stop_tx()
122 hal_writel(value, iobase + GETH_RX_CTL1); in geth_start_rx()
131 hal_writel(value, iobase + GETH_RX_CTL1); in geth_stop_rx()
176 hal_writel(value, iobase + GETH_TX_CTL1); in geth_mac_init()
185 hal_writel(value, iobase + GETH_RX_CTL1); in geth_mac_init()
214 hal_writel(value, iobase + GETH_TX_CTL0); in geth_mac_enable()
273 hal_writel(value, iobase + GETH_INT_EN); in geth_tx_int_enable()
288 hal_writel(value, iobase + GETH_INT_EN); in geth_tx_int_disable()
293 hal_writel(0, iobase + GETH_INT_EN); in geth_all_int_disable()
[all …]
A Dhal_geth.c239 hal_writel(RX_INT,rt_geth_dev.iobase + GETH_INT_STA); in geth_irq_handler()
246 hal_writel(RX_INT,rt_geth_dev.iobase + GETH_INT_STA); in geth_irq_handler()
250 hal_writel(int_sta_value,rt_geth_dev.iobase + GETH_INT_STA); in geth_irq_handler()
683 hal_writel(value, rt_geth_dev.iobase + GETH_BASIC_CTL1); in rt_geth_init()
704 …hal_writel((unsigned long)rt_geth_dev.get_buffer_config.dma_desc_tx, rt_geth_dev.iobase + GETH_TX_… in rt_geth_init()
705 …hal_writel((unsigned long)rt_geth_dev.get_buffer_config.dma_desc_rx, rt_geth_dev.iobase + GETH_RX_… in rt_geth_init()
/bsp/allwinner/libraries/sunxi-hal/hal/source/thermal/
A Dhal_thermal.c73 …hal_writel((hal_readl((unsigned long)THS_CALIB) & TEMP_CALIB_MASK) | (cdata << 16), (unsigned long… in hal_ths_calibrate()
75 hal_writel(cdata, (unsigned long)calib_offest); in hal_ths_calibrate()
87 hal_writel(0x10001, (unsigned long)0x020019fc); in hal_ths_init()
95 hal_writel(THS_CTRL_T_ACQ(479), (unsigned long)THS_CTL); in hal_ths_init()
97 hal_writel(THS_FILTER_EN | THS_FILTER_TYPE(1), (unsigned long)THS_MFC); in hal_ths_init()
99 hal_writel(THS_PC_TEMP_PERIOD(58), (unsigned long)THS_PCTL); in hal_ths_init()
101 hal_writel(THS_NUM, (unsigned long)THS_EN); in hal_ths_init()
116 hal_writel(0x0, (unsigned long)0x020019fc); in hal_ths_uninit()
/bsp/allwinner/libraries/sunxi-hal/hal/source/rtc/
A Dhal_rtc.c199 hal_writel(SUNXI_ALRM_IRQ_STA_CNT_IRQ_PEND, in hal_rtc_setaie()
412 hal_writel(0, rtc_dev->base + SUNXI_RTC_HMS); in hal_rtc_settime()
425 hal_writel(time, rtc_dev->base + SUNXI_RTC_HMS); in hal_rtc_settime()
452 hal_writel(date, rtc_dev->base + SUNXI_RTC_YMD); in hal_rtc_settime()
582 hal_writel(0, rtc_dev->base + SUNXI_ALRM_DAY); in hal_rtc_setalarm()
584 hal_writel(0, rtc_dev->base + SUNXI_ALRM_HMS); in hal_rtc_setalarm()
593 hal_writel(alrm, rtc_dev->base + SUNXI_ALRM_HMS); in hal_rtc_setalarm()
614 hal_writel(0, rtc_dev->base + SUNXI_ALRM_DHMS); in hal_rtc_setalarm()
645 hal_writel(0, rtc_dev->base + SUNXI_ALRM_IRQ_EN); in hal_rtc_setalarm()
692 hal_writel(0, rtc_dev->base + SUNXI_ALRM_EN); in hal_rtc_init()
[all …]
/bsp/allwinner/libraries/sunxi-hal/hal/source/ledc/
A Dhal_ledc.c244 hal_writel(reg_val, base_addr + LEDC_CTRL_REG); in ledc_set_length()
279 hal_writel(reg_val, base_addr + LEDC_CTRL_REG); in ledc_set_output_mode()
288 hal_writel(reg_val, base_addr + LEDC_INTC_REG); in ledc_disable_irq()
297 hal_writel(reg_val, base_addr + LEDC_INTC_REG); in ledc_enable_irq()
305 hal_writel(reg_val, base_addr + LEDC_DMA_CTRL_REG); in ledc_set_dma_mode()
313 hal_writel(reg_val, base_addr + LEDC_DMA_CTRL_REG); in ledc_set_cpu_mode()
322 hal_writel(reg_val, base_addr + LEDC_INTS_REG); in ledc_clear_all_irq()
336 hal_writel(reg_val, base_addr + LEDC_CTRL_REG); in ledc_soft_reset()
345 hal_writel(reg_val, base_addr + LEDC_CTRL_REG); in ledc_reset_en()
350 hal_writel(data, base_addr + LEDC_DATA_REG); in ledc_set_data()
[all …]
/bsp/allwinner/libraries/sunxi-hal/hal/source/pwm/
A Dhal_pwm.c100 hal_writel(reg_val, reg_addr); in hal_pwm_clk_src_set()
118 hal_writel(reg_val, reg_addr); in hal_pwm_clk_div_m()
132 hal_writel(reg_val, reg_addr); in hal_pwm_prescal_set()
148 hal_writel(reg_val, reg_addr); in hal_pwm_set_active_cycles()
162 hal_writel(reg_val, reg_addr); in hal_pwm_set_period_cycles()
206 hal_writel(reg_val, reg_addr); in hal_pwm_enable_clk_gating()
244 hal_writel(reg_val, reg_addr); in hal_pwm_porality()
491 hal_writel(temp, PWM_BASE + reg_offset); in hal_pwm_control()
497 hal_writel(value, PWM_BASE + PWM_PCGR); in hal_pwm_control()
505 hal_writel(temp, PWM_BASE + reg_offset); in hal_pwm_control()
[all …]
/bsp/allwinner/libraries/sunxi-hal/hal/source/efuse/
A Defuse.c126 hal_writel(reg_val, (unsigned long)SID_PRCTL); in _efuse_reg_read_key()
129 hal_writel(reg_val, (unsigned long)SID_PRCTL); in _efuse_reg_read_key()
132 hal_writel(reg_val, (unsigned long)SID_PRCTL); in _efuse_reg_read_key()
151 hal_writel(0x1, (unsigned long)EFUSE_HV_SWITCH); in _efuse_program_key()
153 hal_writel(key_value, SID_PRKEY); in _efuse_program_key()
157 hal_writel(reg_val, (unsigned long)SID_PRCTL); in _efuse_program_key()
160 hal_writel(reg_val, (unsigned long)SID_PRCTL); in _efuse_program_key()
163 hal_writel(reg_val, (unsigned long)SID_PRCTL); in _efuse_program_key()
166 hal_writel(0x0, (unsigned long)EFUSE_HV_SWITCH); in _efuse_program_key()
/bsp/allwinner/libraries/sunxi-hal/hal/source/timer/
A Dsunxi_timer.c46 hal_writel((0x1 << timer->timer_id), (unsigned long)TIMER_IRQ_ST_REG); in sunxi_timer_irq_handle()
78 hal_writel(val & ~TIMER_CTL_ENABLE, (unsigned long)TIMER_CTL_REG(timer)); in sunxi_timer_stop()
100 hal_writel(val | TIMER_CTL_ENABLE | TIMER_CTL_RELOAD, (unsigned long)TIMER_CTL_REG(timer)); in sunxi_timer_start()
105 hal_writel(tick, (unsigned long)TIMER_INTVAL_REG(timer)); in sunxi_timer_setup()
162 hal_writel(val & ~TIMER_CTL_ENABLE, (unsigned long)TIMER_CTL_REG(id)); in sunxi_timer_init()
165 hal_writel((0x1 << id), (unsigned long)TIMER_IRQ_ST_REG); in sunxi_timer_init()
183 hal_writel(val, (unsigned long)TIMER_IRQ_EN_REG); in sunxi_timer_init()
A Dhal_avs.c23 hal_writel(val, avs->base + AVS_CNT_CTRL_REG); in hal_avs_continue()
41 hal_writel(val, avs->base + AVS_CNT_CTRL_REG); in hal_avs_pause()
59 hal_writel(val, avs->base + AVS_CNT_CTRL_REG); in hal_avs_disable()
77 hal_writel(val, avs->base + AVS_CNT_CTRL_REG); in hal_avs_enable()
108 hal_writel(counter, avs->base + AVS_CNT_REG(id)); in hal_avs_set_counter()
130 hal_writel(val, avs->base + AVS_CNT_DIV_REG); in hal_avs_set_cnt_div()
/bsp/allwinner/libraries/sunxi-hal/hal/source/lradc/
A Dhal_lradc.c51 hal_writel(reg_val, base_addr + LRADC_CTRL_REG); in lradc_ctrl_set()
60 hal_writel(reg_val, base_addr + LRADC_CTRL_REG); in lradc_ctrl_reset()
69 hal_writel(reg_val, base_addr + LRADC_INTC_REG); in lradc_irq_set()
78 hal_writel(reg_val, base_addr + LRADC_INTC_REG); in lradc_irq_reset()
98 hal_writel(reg_val, base_addr + LRADC_INTS_REG); in lradc_irq_handler()
/bsp/allwinner/libraries/sunxi-hal/hal/source/spi/
A Dhal_spi.c168 hal_writel(reg_val, sspi->base + SPI_TC_REG); in spi_config_dhb()
240 hal_writel(reg_val, sspi->base + SPI_TC_REG); in spi_config_tc()
279 hal_writel(reg_val, sspi->base + SPI_TC_REG); in spi_start_xfer()
288 hal_writel(reg_val, sspi->base + SPI_GC_REG); in spi_enable_bus()
297 hal_writel(reg_val, sspi->base + SPI_GC_REG); in spi_disable_bus()
306 hal_writel(reg_val, sspi->base + SPI_GC_REG); in spi_set_master()
315 hal_writel(reg_val, sspi->base + SPI_GC_REG); in spi_soft_reset()
324 hal_writel(reg_val, sspi->base + SPI_GC_REG); in spi_enable_tp()
341 hal_writel(reg_val, sspi->base + SPI_TC_REG); in spi_ss_owner()
479 hal_writel(reg_val, sspi->base + SPI_BCC_REG); in spi_set_bc_tc_stc()
[all …]
/bsp/allwinner/libraries/sunxi-hal/hal/source/ir/
A Dhal_ir.c70 hal_writel(tmp, reg_base + IR_RXINTS_REG); in ir_clr_intsta()
143 hal_writel(ctrl_reg, reg_base + IR_CTRL_REG); in ir_mode_set()
181 hal_writel(sample_reg, reg_base + IR_SPLCFG_REG); in ir_sample_config()
189 hal_writel(reg_value, reg_base + IR_RXCFG_REG); in ir_signal_invert()
199 hal_writel(0xef, reg_base + IR_RXINTS_REG); in ir_irq_config()
212 hal_writel(irq_reg, reg_base + IR_RXINTE_REG); in ir_irq_config()
/bsp/allwinner/libraries/sunxi-hal/hal/source/dma/
A Dhal_dma.c227 hal_writel(status_l, DMA_IRQ_STAT(0)); in sunxi_dma_irq_handle()
229 hal_writel(status_h, DMA_IRQ_STAT(1)); in sunxi_dma_irq_handle()
722 hal_writel(irq_val, DMA_IRQ_EN(high)); in hal_dma_start()
735 hal_writel(CHAN_START, DMA_ENABLE(chan->chan_count)); in hal_dma_start()
756 hal_writel(CHAN_PAUSE, DMA_PAUSE(chan->chan_count)); in hal_dma_stop()
757 hal_writel(CHAN_STOP, DMA_ENABLE(chan->chan_count)); in hal_dma_stop()
758 hal_writel(CHAN_RESUME, DMA_PAUSE(chan->chan_count)); in hal_dma_stop()
792 hal_writel(irq_val, DMA_IRQ_EN(high)); in hal_dma_chan_free()
825 hal_writel(0, DMA_IRQ_EN(high)); in hal_dma_init()
827 hal_writel(0xffffffff, DMA_IRQ_STAT(high)); in hal_dma_init()
[all …]
/bsp/allwinner/libraries/sunxi-hal/hal/source/gpio/
A Dhal_gpio.c326 hal_writel(1 << status_idx, gpio_desc->membase + reg); in gpio_irq_ack()
367 hal_writel(regval | (mode << index), gpio_desc->membase + reg); in gpio_irq_set_type()
485 hal_writel(reg | arg << shift, gpio_desc->membase + offset); in gpio_conf_set()
718 hal_writel(temp, gpio_desc->membase + POWER_MODE_SEL); in hal_gpio_sel_vol_mode()
725 hal_writel(temp, gpio_desc->membase + POWER_VOL_SEL); in hal_gpio_sel_vol_mode()
769 hal_writel(reg_val, gpio_desc->membase + reg); in hal_gpio_set_debounce()
909 hal_writel(val | (1 << index), gpio_desc->membase + reg); in hal_gpio_irq_enable()
1005 hal_writel(val & ~(1 << index), gpio_desc->membase + reg); in hal_gpio_irq_disable()
1063 hal_writel(0, gpio_desc->membase + in hal_gpio_init()
1066 hal_writel(0xffffffff, gpio_desc->membase + in hal_gpio_init()
/bsp/allwinner/libraries/sunxi-hal/hal/source/eise/
A Dhal_eise.c58 hal_writel(0x00, pHe->eise_base_addr + EISE_INTERRUPT_EN); in eise_interrupt()
131 hal_writel(reg.value, pHe->eise_base_addr + reg.addr); in eise_hal_ctl()
/bsp/allwinner/libraries/sunxi-hal/hal/source/usb/udc/
A Dudc_platform.h276 #define DRV_WriteReg32(addr, data) hal_writel(data, addr)
282 #define USB_DRV_WriteReg32(addr, data) hal_writel(data, addr)
/bsp/allwinner/libraries/sunxi-hal/hal/source/watchdog/
A Dhal_watchdog.c11 #define writel_wdt hal_writel
/bsp/allwinner/libraries/sunxi-hal/include/hal/
A Dsunxi_hal_common.h109 #define hal_writel(value,reg) (*(volatile uint32_t *)(reg) = (value)) macro
/bsp/allwinner/libraries/sunxi-hal/include/hal/sdmmc/
A Dsdio.h47 #define writel hal_writel

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